Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip

Abstract

Floorplanning, as an early stage of the physical design flow, has been extensively studied in literature and developed into several branches. Recently, hierarchical floorplanning is regaining attention due to the rising scale of systems-on-chip, which necessarily requires divide-and-conquer strategies to handle the increasing complexity. This paper introduces a floorplanning scheme targeting hierarchical physical prototyping, answering some of the questions posed by Kahng [8] on classical floorplanning. Our scheme emphasizes practical requirements including runtime scalability, wire length and shape quality. We formulate a new hierarchical floorplanning problem with reduced computational complexity, but without weakening the problem as a global layout optimization. To achieve this goal, a placement seed is taken as input and converted into a slicing floorplan under the given constraints of region area and aspect ratio (region shape). We solve the problem by devising an efficient slicing algorithm with integrated dynamic programming. Implementation of the algorithm shows fast runtime and good quality of result.

A hierarchical approach for generating regular floorplans

“…However, CompaSS ignores connectivity information. [15] applies a recursive slice-and-partition method derived from cell placement strategies.…”

“…For large systems, a flat view makes the floorplanning problem intractable. For this reason, hierarchical methods [16,15] has been proposed and successfully used to reduce this complexity. Hierarchical methods divide the floorplanning problem into multiple subproblems that may be either fully or partially independent from each other, thereby enhancing scalability.…”

“…To allow this reduction, a regular floorplan uses the exact same layout for all replications of a subcircuit. To reduce complexity of timing closure, it is also desirable for all of the adjacent components to be placed in similar relative positions, so that Hierarchy Regularity [5] No Arrays only REGULAY [17] Yes Tiles only DeFer [16] Yes No CompaSS [4] By similarity No [15] Yes No ArchFP [8] Manual Manual HiReg Yes Yes the interconnect geometries are regular and timing analysis is similar. In many-core CMPs, tiled layouts [3] are often used to exploit regularity.…”

Structure discovery techniques for circuit design and process model visualization

“…For large systems, a flat view makes the floorplanning problem intractable. For this reason, hierarchical methods [135,143] has been proposed and successfully used to reduce this complexity. Hierarchical methods divide the floorplanning problem into multiple subproblems that may be either fully or partially independent from each other, thereby enhancing scalability.…”

“…Regularity is more common in the area of physical design for analog circuits, where it is often a strict requirement due to the peculiarities of analog design [15]. However, Hierarchy Regularity [38] No Arrays only REGULAY [145] Yes Tiles only DeFer [143] Yes No CompaSS [37] By similarity No [135] Yes No ArchFP [64] Manual Manual HiReg Yes Yes most of the techniques in analog design involve symmetry properties that are not relevant for maximizing design reusability.…”