Scalable design of microprogrammed digital FIR filter for sensor processing subsystem

Abstract

In this letter, a novel scalable and modular design of direct form sequential finite impulse response (FIR) filter using microprogrammed control unit is proposed that can be efficiently realized in field programmable gate array (FPGA) or application specific integrated circuit (ASIC). The proposed design is suitable for sensor processing subsystem used in wireless sensor network (WSN) nodes. This is demonstrated by evaluating a sample 4-tap FIR filter on various FPGA platforms and ASIC technologies. The evaluation result shows good area/power efficiency and flexibility by using microprogrammed architecture for such applications.

ASIC realization and performance evaluation of scalable microprogrammed FIR filters using Wallace tree and Vedic multipliers

“…The microprogrammed control unit consists of a microprogram counter and microprogram memory. The datapath unit comprises of 2N data (X) and coefficient (W) registers and N-M decoder (M = log 2 N), two N-input multiplexers for selecting the data and coefficients, a multiplier and an adder, a two input multiplexer to control the flow of data from multiplier or accumulator, one 16-bit accumulator and a 16-bit register to latch the data [4]. …”

“…1 shows a general block diagram of direct form FIR filter. The objective of this paper is to further evaluate the performance of both sequential and parallel scalable microprogrammed FIR filters originally proposed in [4] and [5] using Wallace tree and Vedic multipliers. The multipliers are designed using different adders in order to evaluate the performance and the efficiency of the designs.…”

FPGA implementation of scalable microprogrammed FIR filter architectures using Wallace tree and Vedic multipliers

“…The MCU consists of a microprogram counter and microprogram memory. The datapath unit comprises of 2N data (X) and coefficient (W) registers and M-to-N decoder (M = log 2 N), two N-input multiplexers for selecting the data and coefficients, a multiplier and an adder, a two input multiplexer to control the flow of data from multiplier or accumulator, one 16-bit accumulator and a 16-bit register to latch the data [8]. …”

“…Fig. 3 illustrates the parallel architecture of the microprogrammed FIR filter [8]. For example, the datapath microarchitecture of 4-tap parallel FIR filter consists of the following sub-modules:…”

“…The objective of this paper is to extend the work originally proposed in [5][6][7][8] by implementing the sequential and parallel microprogrammed FIR filters using Wallace tree and Vedic multipliers in FPGA and evaluating their performance for different number of taps. The multipliers use different adder configurations such as carry skip and Kogge-Stone.…”