Scalable Block-Based Parallel Lattice Reduction Algorithm for an SDR Baseband Processor

Ahmad, Ubaid; Amin, Amir; Li, Min; Pollin, Sofie; Perre, Liesbet Van der; Catthoor, Francky

doi:10.1109/icc.2011.5963386

Cited by 7 publications

(3 citation statements)

References 14 publications

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“…The interconnection topology of PEA also has a great variety, which could be further categorized into two types [9] according to the interconnection scheme: 1) array-based PEA [6], [10]- [12]; and 2) row-based PEA [8], [13], [14]. The routing topologies in array-based CGRAs are usually mesh or mesh-plus, where each PE could connect to its four or eight neighbors.…”

Section: A Target Architecture Overview and Mapping Methodsmentioning

confidence: 99%

Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures

Liu

Yin

Peng

et al. 2015

IEEE Trans. VLSI Syst.

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Coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their flexibility and efficiency. Loops in applications are often mapped onto CGRAs for acceleration, and the mapping of loops onto CGRA is quite a challenging work due to the parallel execution paradigm and constrained hardware resource. To map loops onto CGRAs efficiently, it is important to transform loops into pieces that obey hardware resource constraints with less overhead (e.g., communication and configuration overhead). In this paper, we tackle this problem by establishing a performance optimization problem, including loop transformation and backend placing and routing. A novel searching strategy is also designed to find the optimal result efficiently. Finally, we built a complete flow of mapping loop nests onto CGRA. Experiment results on most kernels of the Polybench show that our proposed approach can improve the performance of the kernels by 42% on average, as compared with the state-of-the-art methods. The runtime complexity of our approach is also acceptable.

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Section: A Target Architecture Overview and Mapping Methodsmentioning

confidence: 99%

Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures

Liu

Yin

Peng

et al. 2015

IEEE Trans. VLSI Syst.

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“…In addition, if a sub-problem could benefit from a multi-threaded environment it can be regarded as a second level of parallelism. Previous parallel LR implementations, such as the ones presented in [1,2,12], have focused only on multi-core architectures. The main drawback of the low number of threads offered by modern CPUs (compared to GPUs) is that low level parallelism can not be efficiently exploited.…”

Section: Problem Descriptionmentioning

confidence: 99%

“…Furthermore, the excessive use of shared memory is decreasing the occupancy, resulting in performance degradation. Shared buffers buf 1 …”

Section: Algorithm 1 Cr-as-lll Openmp Pseudocodementioning

confidence: 99%

High performance lattice reduction on heterogeneous computing platform

et al. 2014

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Jozsa, CM.; Domene Oltra, F.; Vidal Maciá, AM.; Piñero Sipán, MG.; González Salvador, A. (2014). High performance lattice reduction on heterogeneous computing platform. Journal of Supercomputing. 70(2):772-785. doi:10.1007/s11227-014-1201-2. Abstract The lattice reduction (LR) technique has become very important in many engineering fields. However, its high complexity makes difficult its use in real-time applications, especially in applications that deal with large matrices. As a solution, the Modified Block LLL (MB-LLL) algorithm was introduced in [10], where several levels of parallelism were exploited: (i.) coarse-grained parallelism was achieved by applying the block-reduction concept presented in [15] and (ii.) fine-grained parallelism was achieved through the Cost Reduced All-Swap LLL (CR-AS-LLL) algorithm introduced in [10].In this paper, we present the Cost Reduced MB-LLL (CR-MB-LLL) algorithm, which allows to significantly reduce the computational complexity of the MB-LLL by allowing the relaxation of the first LLL condition while executing the LR of submatrices, resulting in the delay of the GS coefficients update and by using less costly procedures during the boundary checks. The effects of complexity reduction and implementation details are analyzed and discussed for several architectures. A mapping of the CR-MB-LLL on a heterogenenous platform is proposed and it is compared with implementations running on a dynamic parallelism enabled GPU and a multi-core CPU. The mapping on the architecture proposed allows a dynamic scheduling of kernels where the overhead introduced is hidden by the use of several CUDA streams. Results show that the execution time of the CR-MB-LLL algorithm on the heterogeneous platform outperforms the multi-core CPU and it is more efficient than the CR-AS-LLL algorithm in case of large matrices.

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