Scalable and Unified Digit-Serial Processor Array Architecture for Multiplication and Inversion Over GF( $2^{m}$ )

Efficient parallel semi-systolic array structure for multiplication and squaring in GF(2<i>^m</i>)

“…2) allocating a time value to each node in the DG using a specific timing or scheduling function. 3) mapping several nodes of the DG to a processing element (PE) to form the systolic/semi-systolic array [20,25,26,27,28,29,30]. The DG of the unified multiplication and squaring algorithm over GFð2 m Þ can be extracted from the recursive Eqs.…”

“…The DG of the unified multiplication and squaring algorithm over GFð2 m Þ can be extracted from the recursive Eqs. 15, (24), (25), (26), (27), (30), and (31). The extracted DG based on these equations is shown in Fig.…”

“…The upper part consists of the upper l rows of the DG (rows with the light red nodes) and it computes the coefficients of C, H, G, V, U according to Eqs. (15), (24), (25), (26), (27), respectively. The lower part consists of the last row of the DG (row with the brown nodes) and it computes the coefficients of P and S according to Eqs.…”

New systolic array architecture for finite field division

“…This approach starts by obtaining the dependency graph (DG) for the intended algorithm and assigning a time value to each node in the DG using a scheduling function as explained by authors in [14,15,16,17,18,20]. The approach ends by projecting several nodes of the DG to a processing element (PE) to constitute the systolic array [14,17,19,20,21,22].…”

“…The systolic array architecture can be extracted by choosing the scheduling vector S ¼ ½1 0 and the projection vector P ¼ ½0 1 T for the DG. These vectors are obtained from applying the approach previously reported by authors in [14,17,20,21,22]. Fig.…”