2018
DOI: 10.1145/3233183
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Scalable Analysis for Multi-Scale Dataflow Models

Abstract: DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal… Show more

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Cited by 6 publications
(5 citation statements)
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“…7 (c), the throughput is 1 65 and the latency, relative to the period equalling the inverse of the throughput, is 65. We omit the details of the computation, referring the reader to [40]. But the results should not be surprising given the timing analysis of the scenario execution given earlier.…”
Section: ) System Mapping and Mapping Configurationsmentioning
confidence: 96%
See 1 more Smart Citation
“…7 (c), the throughput is 1 65 and the latency, relative to the period equalling the inverse of the throughput, is 65. We omit the details of the computation, referring the reader to [40]. But the results should not be surprising given the timing analysis of the scenario execution given earlier.…”
Section: ) System Mapping and Mapping Configurationsmentioning
confidence: 96%
“…In this subsection, we summarise the relevant definitions for our analysis. For detailed explanations, the reader is referred to [40].…”
Section: ) System Mapping and Mapping Configurationsmentioning
confidence: 99%
“…The HLS pragma is compatible with the free-running mode and we use both in this paper. Yet, most Xilinx dataflow examples are single-rate ones not benefiting from the free-running mode, such as Xilinx version of Gaussian difference 3 .…”
Section: Hls Free-running Kernelsmentioning
confidence: 99%
“…In [3], authors develop a method to compute the maximum achievable throughput of a dataflow graph of actors similar to FPGA kernels. Their analysis takes benefit of an extra Finite State Machine (FSM) separating the kernel phases into an initial read (rush-in), a cyclic computation phase and a final write (rush-out).…”
Section: Sdf Analysis For Buffer Sizingmentioning
confidence: 99%
“…The execution times for the tasks RoID, RoIP, RoIM, C and A are e d , e p , e m , e c and e a respectively. A scenarioaware dataflow graph [14] (see Fig. 3) is composed of: (i) a set of scenarios that model the workload variations (and are hence called workload scenarios); and (ii) a language that describes a set of infinite scenario (switching) sequences.…”
Section: A Ibc Application Modelmentioning
confidence: 99%