Scalability Studies of the BLASTn Scan and Ungapped Extension Functions

Datta, Siddhartha; Sass, Ron

doi:10.1109/reconfig.2009.60

Cited by 3 publications

(2 citation statements)

References 19 publications

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“…The BLAST query is encoded into the 8 KByte local block. Researchers have implemented BLAST on FPGAs to demonstrate impressive speedups [19]; however, previous work [20,21] has shown that bandwidth requirements for BLAST limit the scalability such that a common bus interconnect is insufficient for transferring databases to each BLAST core as well as being used for off-chip memory lookups. Specifically, each BLAST core can sustain database input rates of 3.2 GB/s.…”

Section: Kernel Performancementioning

confidence: 99%

Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip

Kritikos

Schmidt

Sass

et al. 2012

International Journal of Reconfigurable Computing

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The reconfigurable data-stream hardware software architecture (Redsharc) is a programming model and network-on-a-chip solution designed to scale to meet the performance needs of multi-core Systems on a programmable chip (MCSoPC). Redsharc uses an abstract API that allows programmers to develop systems of simultaneously executing kernels, in software and/or hardware, that communicate over a seamless interface. Redsharc incorporates two on-chip networks that directly implement the API to support high-performance systems with numerous hardware kernels. This paper documents the API, describes the common infrastructure, and quantifies the performance of a complete implementation. Furthermore, the overhead, in terms of resource utilization, is reported along with the ability to integrate hard and soft processor cores with purely hardware kernels being demonstrated.

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Section: Kernel Performancementioning

confidence: 99%

Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip

Kritikos

Schmidt

Sass

et al. 2012

International Journal of Reconfigurable Computing

Self Cite

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“…BLAST is a bioinformatics application that performs DNA comparisons. [14]. The BLAST hardware kernel is a reimplementation of this algorithm.…”

Section: B Scalabilitymentioning

confidence: 99%

Merging Programming Models and On-chip Networks to Meet the Programmable and Performance Needs of Multi-core Systems on a Programmable Chip

Schmidt

Kritikos

Anderson

et al. 2010

2010 International Conference on Reconfigurable Computing and FPGAs

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The REconfigurable Data-Stream Hardware Software ARChitecture (Redsharc) is a programming model and networkon-a-chip solution designed to scale to meet the performance needs of multi-core systems on a programmable chip. Redsharc uses an abstract API that allows programmers to develop systems of simultaneously executing kernels, in software or hardware, that communicate over a seamless interface. To support high performance systems with numerous hardware kernels, Redsharc incorporates two on-chip networks that directly mimic the API. Our results show that Redsharc running at 200 MHz, 32-bit data widths can achieve 800 MBps per stream from hardware to hardware, 480 MBps for a software to hardware stream, and between 20 MBps and 400 MBps for random access data in blocks, regardless of the number of kernels in the system.

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Investigation into scaling I/O bound streaming applications productively with an all-FPGA cluster

et al. 2012

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Scalability Studies of the BLASTn Scan and Ungapped Extension Functions

Cited by 3 publications

References 19 publications

Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip

Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip

Merging Programming Models and On-chip Networks to Meet the Programmable and Performance Needs of Multi-core Systems on a Programmable Chip

Investigation into scaling I/O bound streaming applications productively with an all-FPGA cluster

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