SC filter for RF sampling and downconversion with wideband image rejection

Andersson, Stefan; Konopacki, J.; Dąbrowski, Jerzy; Svensson, Christer

doi:10.1007/s10470-006-7833-2

Cited by 8 publications

(3 citation statements)

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“…Prior to A/Dconversion the sampled signal is decimated and bandlimited. Particularly, the image bands introduced by the decimation process are removed by this filter [7][8][9]. Special techniques are used to mitigate the effect of 1/f noise and the wideband noise folding in the SC filter.…”

Section: Architecture Level Designmentioning

confidence: 99%

“…The poles in (8) have been cancelled and one can expect the corresponding frequency response less susceptible to the parameter variations. Another advantage is to spread the decimation process so that each block in cascade operates at one half of the frequency of preceding block.…”

Section: Rf-sampling Mixermentioning

confidence: 99%

“…The implementation of the decimation filter (both I and Q) directly follows from (8). It consists of four cascaded sections as shown in Fig.…”

Section: Rf-sampling Mixermentioning

confidence: 99%

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Multiband RF-sampling receiver front-end with on-chip testability in 0.13 μm CMOS

Ramzan

Andersson

Dąbrowski

et al. 2009

Analog Integr Circ Sig Process

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In this paper a flexible RF-sampling front-end primarily intended for WLAN standards operating in the 2.4 GHz and 5-6 GHz bands is presented. The circuit is implemented with on-chip Design for Test (DfT) features in 0.13 lm CMOS process. The front-end consists of a wideband LNA, a sampling IQ down-converter implemented as switched-capacitor decimation filter, test attenuator (TA), and RF detectors. The architecture is generic and scalable in frequency. It can operate at a sampling frequency up to 3 GHz and RF carrier up to 6 GHz with 29 subsampling. The selectable decimation factor of 8 or 16 makes the A/D conversion feasible. The frequency response, linearity, and NF of the whole frontend have been measured. The power consumption of complete RF front-end is 176 mW. The on-chip DfT features are helpful in reduction of overall test cost and time in volume production. The measurement results show the feasibility of DfT approach for multiband radio receiver design using standard CMOS process.

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Section: Architecture Level Designmentioning

confidence: 99%

Section: Rf-sampling Mixermentioning

confidence: 99%