Saturn: a terabit packet switch using dual round robin

Jiang, Chao

doi:10.1109/35.888261

Cited by 142 publications

(59 citation statements)

References 11 publications

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“…H.J. Chao et.al, 2001 [5] proposed a model by designing a high capacity packet switch (eg. Multiple terabits/second) that: (1) supports individual line rates in excess of the speeds of available electronic memory and is capable of supporting the same qualities and service as an output-queued switch and from a more practical point of view, the arbitration should be separated from the output packet scheduling to keep the implementation and time complexities reasonable.…”

Section: Iiliterature Surveymentioning

confidence: 99%

Packet Switching – Queuing Architecture: A Study

Bahl¹

2015

IJIRCCE

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ABSTRACT:In this paper, the packet switching architecture with output queuing is used. Here the switch is internally non-blocking, but if packets destined to same outputs, output blocking will occur and (even if there are output queues) has a capacity of N*N2 .An exact model of the switch has been developed which can be used to determine the blocking performance of the switch and obtain both its throughput and packet loss characteristics. In this architecture, each line card is connected by a dedicated point to point link to the central switch fabric. Two structures can be classified as Centralized and Distributed. Buffer arrangements are also categorized into output queued and combined input-output queued switches and hardware complexity of OQ, VOQ are also discussed. KEYWORDS:IQ Switches, OQ Switches, VOQ Switches, Switch Fabric. I.INTRODUCTIONOver the past decade, data communication has been revolutionized by a radically new technology called Packet Switching. Packet switched routers need buffers during times of congestion. Buffer arrangements can be placed on inputs and outputs within the switch fabric. A major challenge connected to high-speed switching is related today to switch design that requires the best possible ease of implementation and good performance. The main functions of Switching are: (i) manage packet buffering while selecting packets to transmit each time to avoid contentions and cell loss. (ii) Routing packets from their incoming ports to their destination ports. To avoid contentions and cell loss, the incoming packets are stored in buffers. These buffers can be in inputs, in outputs, in inputs and outputs or shared by inputs and outputs. Although, a lot of existing switches use the shared buffers techniques. In OQ (Output Queue) strategy, all incoming cells at the input are allowed to arrive at the output port and they are served using FIFO (First in First Out) discipline. In this strategy, there is 100% throughput and there is an internal speedup of order of N(impractical for large N) [1].An output buffered switch can be more complex than an input buffered switch because the switch fabric must operate at much higher speed to reduce the probability of cell loss.The IQ (Input Queue) switch can transfer at most one packet from an input and at most one packet to an output in a slot. At the beginning of a slot, more than one HOL (Head of Line Blocking) cells from the input queues have the same destination, and then only one of them is switched and transmitted on the output link in the slot. These switches are easy to implement and throughput is limited to 58.6% under uniform traffic. The other HOL cells continue to be queued at their inputs. Thus, packets in an IQ switch can experience HOL blocking, in which a blocked HOL cell blocks the cells behind it in the input FIFO queue even though the destination ports of these other cells are free and are idling. One of the proposed solution for IQ switches which is VOQ. In this, the main aim is to overcome HOL blocking as there is no speed up require...

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Section: Iiliterature Surveymentioning

confidence: 99%

Packet Switching – Queuing Architecture: A Study

Bahl¹

2015

IJIRCCE

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“…DRR's one difference from round robin algorithm is that if a queue was not able to send a packet in the previous round because of its packet size was too large, the previous quantum is added to the next round. Another round robin based study is SATURN [10]. SATURN uses simple dual round robin arbitration scheme to schedule packets.…”

Section: Related Workmentioning

confidence: 99%

A New Packet Scheduling Algorithm for Real-Time Multimedia Streaming

Şimşek

Doğan

Akçayol

2017

NPA

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Delivering the real-time services over converged networks is a big challenge. Real-time services need to high Quality of Service (QoS). For this purpose, bandwidth reservation and packet prioritization techniques are used. Thus, real-time data packets can be reached to their targets with minimum delays and losses.But, this situation creates unintended consequences for other internet services such as HTTP and FTP. In this case, establishing a balance between the real-time services and the other services is a must. In this study we introduce a new research question: how to transport real-time multimedia IP packets just in Network Protocols and Algorithms ISSN 1943-3581 2017 www.macrothink.org/npa 29 time? Just in time means that transportation of the packets neither early, nor late. For this purpose we developed a scheduling/prioritizing algorithm called just in time transport (JITT). Following a cross-layer design approach, JITT controls delay and jitter over whole communication path. We evaluated JITT on the different simulations and one experimental testbed for performance analysis. Our findings support that JITT provides stable delay and low jitter and transports the packets nearly just in time.

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“…Chao developed a path-disjoint ATM switch by using multiple switch planes [Ch00]. Each switch plane consists of a matrix interconnection of crosspoint chips (XPCs).…”

Section: Paths Disjoint In Spacementioning

confidence: 99%

The Folded Hypercube ATM Switches

Park

Davis

2001

Networking — ICN 2001

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Over the past few years, many high performance asynchronous transfer mode (ATM) switches have been proposed. The majority of these switches have high performance but also high hardware complexity. Therefore, there is a need for switch designs with low complexity and high performance. This research proposes three new ATM switches based on the folded hypercube network (FHC). The performance of the three architectures are studied using a network model and simulation. The major performance parameters measured are the cell loss rate and cell delay time through the switch under uniform, normal, and bursty traffic patterns. To guarantee faster switching of time-sensitive cells, the routing algorithm of the three switches uses a priority scheme that gives higher precedence to the time-sensitive cells. Also, an output buffer controller is designed to manage the buffers in a fair manner. The three proposed switch architectures have lower complexity while providing equivalent or better switching performance compared to other more complex ATM switches described in the literature. This research shows a new approach to designing ATM switches by using the FHC as the switching fabric for the first time instead of using the crossbar, multi-path, or Banyan-based switching fabrics.iii DedicationsAfter a long and painful fight against cancer, my grandfather passed away on Christmas Eve, 1999.He deeply wanted to, but was not able to see me receive the doctorate degree. I was blessed to receive his continual love and support for me. I hope he is looking down on me from heaven feeling proud.This dissertation is dedicated to my grandfather, Wookyu Park, in his loving memory.

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Saturn: a terabit packet switch using dual round robin

Cited by 142 publications

References 11 publications

Packet Switching – Queuing Architecture: A Study

Packet Switching – Queuing Architecture: A Study

A New Packet Scheduling Algorithm for Real-Time Multimedia Streaming

The Folded Hypercube ATM Switches

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