SAT-Hard Cyclic Logic Obfuscation for Protecting the IP in the Manufacturing Supply Chain

Abstract

State-of-the-art attacks against cyclic logic obfuscation use satisfiability solvers that are equipped with a set of cycle avoidance clauses. These cycle avoidance clauses are generated in a pre-processing step and define various key combinations that could open or close cycles without making the circuit oscillating or stateful. In this paper, we show that this preprocessing step has to generate cycle avoidance conditions on all cycles in a netlist, otherwise, a missing cycle could trap the solver in an infinite loop or make it exit with an incorrect key. Then, we propose several techniques by which the number of cycles is exponentially increased as a function of the number of inserted feedbacks. We further illustrate that when the number of feedbacks is increased, the pre-processing step of the attack faces an exponential increase in complexity and runtime, preventing the correct composition of cycle avoidance clauses in a reasonable time. On the other hand, if the pre-processing is not concluded, the attack formulated by the satisfiability solver will either get stuck or exit with an incorrect key. Hence, when the cyclic obfuscation under the conditions proposed in this paper is implemented, it would impose an exponentially difficult problem for the satisfiability solver based attacks.

From Cryptography to Logic Locking: A Survey on the Architecture Evolution of Secure Scan Chains

“…Hence, in some recent obfuscation techniques, the behavioral properties of the circuit (such as timing) have been targeted that cannot be translated to CNF [29]. In some other techniques, the key-programmable cycles are added into the design, which traps the SAT solver in an infinite loop [26]- [28], [37], [38]. Although these solutions defeat the SAT attack, further investigation shows that this breed of obfuscation techniques is already broken using SMT attack [14], [45], timingSAT [46], and SAT-based attacks on cyclic obfuscation [12], [13], [47].…”

Area efficient camouflaging technique for securing IC reverse engineering

“…To overcome this, the authors propose printed camouflaged logic cells with negligible overhead. In [ 31 ], a cyclic obfuscation under different cycle conditions is proposed to show the complexity level of RE with an exponentially increasing time.…”

NNgSAT

“…Some techniques try to lock the timing of the circuit using either custom-designed cell or flip-flop relocation [13,58], which cannot be modeled by the SAT solver. In some other techniques, since the SAT attack is only applicable to DAG, the combinational cycles are added for obfuscation purposes, which might trap the iterative structure of the SAT attack in an infinite loop, or it leads to an incorrect key [4,5,28,47,48]. Also, since the SAT solver is only applicable to combinational logic circuits, and the access to the scan chain is required for the SAT attack, some techniques try to block any unauthorized access to the scan chain [14,17,18,42,49,51,52] to resist against the SAT attack.…”