Sara

Song, Yang; Alavoine, Olivier; Lin, Bill

doi:10.1145/3195970.3196110

Cited by 2 publications

(5 citation statements)

References 9 publications

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“…Detailed simulation configurations are depicted in Table 1. Memory traffic of real-time cores is produced in the same way as in Reference [28]. Specifically, memory requests are generated per-core and per-DMA according to memory specifications of Qualcomm Snapdragon 845 [25].…”

Section: Methodsmentioning

confidence: 99%

“…Specifically, in these approaches packets are categorized in distinct frames or classes that are served based on their priority levels. There have also been works [28,32] adjusting priority levels of network packets according to requestors' QoS experiences. In Reference [28], the priority of a packet is set to reflect the requestor's actual performance relative to its target QoS.…”

Section: Integrating Qos Supportmentioning

confidence: 99%

“…There have also been works [28,32] adjusting priority levels of network packets according to requestors' QoS experiences. In Reference [28], the priority of a packet is set to reflect the requestor's actual performance relative to its target QoS. The resulting priority level is attached to the packet and can be used for priority-based round-robin (specified below) in the memory subsystem.…”

Section: Integrating Qos Supportmentioning

confidence: 99%

“…To evaluate memory efficiency improvement under QoS support, we implement the Localityaware QoS policy from Section 3.3, as well as the QoS-aware RR policy. In our implementation, QoS priority levels are generated at source as proposed in Reference [28]. The latency sensitivity and the random memory access pattern make the DSP an ideal example for the demonstration of achieving QoS target during locality-aware forwarding.…”

Section: Row-buffer Locality With Qos Supportmentioning

confidence: 99%

“…Priority levels are calculated at sources according to end-to-end QoS of real-time cores. More details can be found in Reference[28].…”

mentioning

confidence: 99%

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Improving Memory Efficiency in Heterogeneous MPSoCs through Row-Buffer Locality-aware Forwarding

Song

Lin

2020

ACM Trans. Archit. Code Optim.

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In heterogeneous multicore systems, the memory subsystem plays a critical role, since most core-to-core communications are conducted through the main memory. Memory efficiency has a substantial impact on system performance. Although memory traffic from multimedia cores generally manifests high row-buffer locality, which is beneficial to memory efficiency, the locality is often lost as memory streams are forwarded through networks-on-chip (NoC). Previous studies have discussed the techniques that improve memory visibility to reveal scattered row-buffer hit opportunities to the memory scheduler. However, extending local memory visibility introduces little benefit after the locality has been severely diluted. As the alternative approach, preserving row-buffer locality in the NoC has not been well explored. What is worse, it remains to be studied how to perform network traffic scheduling with the awareness of both memory efficiency and quality-of-service (QoS). In this article, we propose a router design with embedded row-index caches to enable locality-aware packet forwarding. The proposed design requires minor modifications to existing router microarchitecture and can be easily implemented with priority arbiters to integrate QoS support. Extensive evaluations show that the proposed design achieves higher memory efficiency than prior memory-aware routers, in addition to providing QoS support. On basis of extant QoS-aware routers, locality-aware forwarding helps to increase row-buffer hits by 58.32% and reduce memory latency by 14.45% on average. It also introduces a net reduction in DRAM and NoC energy cost by 27.82%.

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Section: Methodsmentioning

confidence: 99%

Section: Integrating Qos Supportmentioning

confidence: 99%