SAR ADC design using Golden ratio weight algorithm

Kobayashi, Yutaro; Shibuya, Shohei; Arafune, Takuya; Sasaki, Shu; Kobayashi, Haruo

doi:10.1109/iscit.2015.7458367

Cited by 8 publications

(3 citation statements)

References 3 publications

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“…The beautiful characteristics of its "error correction range" were shown. Also, several related results were found [52,53]. Fig.…”

Section: Fibonacci-sequence Weighted Sar Adcmentioning

confidence: 70%

How the Author's Group Came Up with Ideas in Analog/Mixed-Signal Circuit and System Area

KOBAYASHI

2024

IEICE Trans. Fundamentals

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This article reviews the author's group research achievements in analog/mixed-signal circuit and system area with introduction of how they came up with the ideas. Analog/mixed-signal circuits and systems have to be designed as well-balanced in many aspects, and coming up ideas needs some experiences and discussions with researchers. It is also heavily dependent on researchers. Here, the author's group own experiences are presented as well as their research motivations.

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“…The beautiful characteristics of its "error correction range" were shown. Also, several related results were found [52,53]. Fig.…”

Section: Fibonacci-sequence Weighted Sar Adcmentioning

confidence: 70%

How the Author's Group Came Up with Ideas in Analog/Mixed-Signal Circuit and System Area

KOBAYASHI

2024

IEICE Trans. Fundamentals

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“…The basic circuits of the proposed ADC are shown and its operation is confirmed with LTspice simulation with TSMC 0.18 um CMOS process parameters. We close this paper by remarking that the proposed ADC can be extended to a non-binary weighted structure [13,14,15,16,17,18]; since it can have some redundancy, the decision mistakes of the upper bits can be digitally corrected if the lower bits are obtained correctly, the upper bit generation circuits can be designed with minimum size and power. This would be the next project.…”

Section: Discussionmentioning

confidence: 97%

“…The ADC is a key circuit for interface between analog and digital worlds [1,2,3]. Much attention has been paid to the SAR ADC due to small chip area and low power as well as no need for operational amplifier [4,5,6,7,8,9,10,11,12,13,14,15,16,17,18], and its figure of merits (FOM) has been improved. The Hopfield network has been investigated as an ADC architecture for several tens of years [19,20,21,22,23,24], but it has not been widely used in practice.…”

Section: Introductionmentioning

confidence: 99%

Asynchronous capacitive SAR ADC based on Hopfield network

Bai

Katayama

Yao

et al. 2022

IEICE Electron. Express

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This letter revisits a Hopfield network for an SAR ADC configuration, which enables low voltage, low power and fast operation with small circuitry. It employs an asymmetrical Hopfield network to avoid local minimum, and it uses capacitors and switches instead of very large resistors. Our N-bit SAR ADC uses N chopper-type comparators with asynchronous parallel operation, which is different from the conventional asynchronous SAR ADC employing only one comparator. It requires only the sampling clock for each input data sampling; no internal high frequency clock is required. Its AD conversion time is determined only by the comparator delays and the capacitor charge/discharge settling times; hence it is very fast and the AD conversion latency is only one or two clock cycles. Its operation is verified with SPICE simulations.

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