SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15,000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency

Miro-Panades, Ivan; Tain, Benoit; Christmann, Jean-Frédéric; Coriat, David; Lemaire, R.; Jany, Clement; Martineau, Baudouin; Chaix, Fabrice; Quelen, Anthony; Pluchart, Emmanuel; Noël, Jean-Philippe; Boumchedda, Reda; Makosiej, Adam; Montoya, Maxime; Bacles-Min, Simone; Philippe, Jean-Marc; Valentian, Alexandre; Heitzmann, Frédéric; Beigné, Edith; Clermidy, Fabien

doi:10.1109/vlsicircuits18222.2020.9163000

Cited by 20 publications

(19 citation statements)

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“…Table 2 shows a comparison with recently published IoT end-nodes and fully programmable clusters. Compared to traditional single-core IoT end nodes [29], [30], the proposed work delivers significantly better performance and efficiency thanks to the exploitation of parallelism. Compared to similar fully programmable multi-core IoT endnodes [23], [31], implemented in 40nm and 22nm technology nodes, respectively, the proposed SoC delivers similar performance and energy efficiency on an 8-bit format, despite the less scaled technology node used for its implementation.…”

Section: Comparison With the State-of-the-artmentioning

confidence: 99%

Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

Ottavi¹,

Garofalo²,

Tagliavini³

et al. 2022

Preprint

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Computationally intensive algorithms such as Deep Neural Networks (DNNs) are becoming killer applications for edge devices. Porting heavily data-parallel algorithms on resource-constrained and battery-powered devices poses several challenges related to memory footprint, computational throughput, and energy efficiency. Low-bitwidth and mixed-precision arithmetic have been proven to be valid strategies for tackling these problems. We present Dustin, a fully programmable compute cluster integrating 16 RISC-V cores capable of 2-to 32-bit arithmetic and all possible mixed-precision permutations. In addition to a conventional Multiple-Instruction Multiple-Data (MIMD) processing paradigm, Dustin introduces a Vector Lockstep Execution Mode (VLEM) to minimize power consumption in highly data-parallel kernels. In VLEM, a single leader core fetches instructions and broadcasts them to the 15 follower cores. Clock gating Instruction Fetch (IF) stages and private caches of the follower cores leads to 38% power reduction with minimal performance overhead (< 3%). The cluster, implemented in 65 nm CMOS technology, achieves a peak performance of 58 GOPS and a peak efficiency of 1.15 TOPS/W.

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Section: Comparison With the State-of-the-artmentioning

confidence: 99%

Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

Ottavi¹,

Garofalo²,

Tagliavini³

et al. 2022

Preprint

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“…More in line with the target of a flexible and configurable smart sensing platform are Miro-Panades et al; They present an asynchronous RISC processor with an integrated wake-up radio receiver for efficient low-latency wake-up from several external and internal triggers. While their architecture achieves outstanding reaction time to interrupts without the need for a high-frequency clock, the wake-up circuitry lacks the interface and compute capability to perform actual data processing for data input pattern dependent wake-up [9]. Wang et al present a configurable WuC resembling the work in [17] that combines an LC-ADC with a set of asynchronous detector blocks to extract low-level signal properties like peak amplitude, slope, or time interval between peaks.…”

Section: Related Workmentioning

confidence: 99%

“…An energy proportional sensor data processing scheme, where a wake-up circuit (WuC) detects patterns of interest and aggressively duty cycles other circuitry is a viable solution to drastically reduce average power consumption [9,10]. While there are numerous WuCs, e.g., for biosignal anomaly detection, sound/keyword spotting, incoming radio transmissions in the µW range, all of these solutions are highly applicationspecific.…”

Section: Introductionmentioning

confidence: 99%

A 5 μW Standard Cell Memory-based Configurable Hyperdimensional Computing Accelerator for Always-on Smart Sensing

Eggimann¹,

Rahimi²,

Benini³

2021

Preprint

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Hyperdimensional computing (HDC) is a braininspired computing paradigm based on high-dimensional holistic representations of vectors. It recently gained attention for embedded smart sensing due to its inherent error-resiliency and suitability to highly parallel hardware implementations. In this work, we propose a programmable all-digital CMOS implementation of a fully autonomous HDC accelerator for always-on classification in energy-constrained sensor nodes. By using energyefficient standard cell memory (SCM), the design is easily crosstechnology mappable. It achieves extremely low power, 5 µW in typical applications, and an energy-efficiency improvement over the state-of-the-art (SoA) digital architectures of up to 3× in postlayout simulations for always-on wearable tasks such as EMG gesture recognition. As part of the accelerator's architecture, we introduce novel hardware-friendly embodiments of common HDC-algorithmic primitives, which results in 3.3× technology scaled area reduction over the SoA, achieving the same accuracy levels in all examined targets. The proposed architecture also has a fully configurable datapath using microcode optimized for HDC stored on an integrated SCM based configuration memory, making the design "general-purpose" in terms of HDC algorithm flexibility. This flexibility allows usage of the accelerator across novel HDC tasks, for instance, a newly designed HDC applied to the task of ball bearing fault detection.

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“…Table VIII shows a comparison with a wide range of programmable embedded computing platforms, including RISC-V based vector processors for transprecision FP computations [37] and low-power IoT computing systems [38] exploiting either parallelism [11], heterogeneity [39], or both [40] to address the high computing requirements of emerging NSAA applications and DNNs.…”

Section: Comparison With Soamentioning

confidence: 99%

Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode

Rossi,

Conti,

Eggimann

et al. 2021

Preprint

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Internet-of-Things requires end-nodes with ultra-low-power always-on capability for a long battery lifetime, as well as high performance, energy efficiency, and extreme flexibility to deal with complex and fast-evolving near-sensor analytics algorithms (NSAAs). We present Vega, an IoT end-node SoC capable of scaling from a 1.7 µW fully retentive cognitive sleep mode up to 32.2 GOPS (@ 49.4 mW) peak performance on NSAAs, including mobile DNN inference, exploiting 1.6 MB of state-retentive SRAM, and 4 MB of non-volatile MRAM. To meet the performance and flexibility requirements of NSAAs, the SoC features 10 RISC-V cores: one core for SoC and IO management and a 9-cores cluster supporting multi-precision SIMD integer and floating-point computation. Vega achieves SoAleading efficiency of 615 GOPS/W on 8-bit INT computation (boosted to 1.3TOPS/W for 8-bit DNN inference with hardware acceleration). On floating-point (FP) compuation, it achieves SoAleading efficiency of 79 and 129 GFLOPS/W on 32-and 16bit FP, respectively. Two programmable machine-learning (ML) accelerators boost energy efficiency in cognitive sleep and active states, respectively.

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SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15,000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency

Cited by 20 publications

References 0 publications

Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

A 5 μW Standard Cell Memory-based Configurable Hyperdimensional Computing Accelerator for Always-on Smart Sensing

Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode

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