2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture 2010
DOI: 10.1109/micro.2010.24
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Sampling Dead Block Prediction for Last-Level Caches

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Cited by 168 publications
(135 citation statements)
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“…Figure 4 shows that for a 16-way 2MB LLC, the optimal bypass with LRU (LRU+OB) reduces average misses by 23.5% compared to LRU, and it bridges roughly four-fifths of the gap between LRU and OPT+B. Compared to other recent proposals like DRRIP [12] and SDBP [19], it outperforms them dramatically. Although it is still impractical to implement the optimal bypass due to the need of future information, we can learn the past behavior of the optimal bypass to predict its future behavior.…”
Section: Motivationmentioning
confidence: 98%
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“…Figure 4 shows that for a 16-way 2MB LLC, the optimal bypass with LRU (LRU+OB) reduces average misses by 23.5% compared to LRU, and it bridges roughly four-fifths of the gap between LRU and OPT+B. Compared to other recent proposals like DRRIP [12] and SDBP [19], it outperforms them dramatically. Although it is still impractical to implement the optimal bypass due to the need of future information, we can learn the past behavior of the optimal bypass to predict its future behavior.…”
Section: Motivationmentioning
confidence: 98%
“…For a 1024-entry BDCT, the lower 10 bits of PC are used to index the BDCT. Like all PC based methods [17,19,20,21,23,35,37], the shortened PC is delivered along with the request through the cache hierarchies.…”
Section: Implementation Detailsmentioning
confidence: 99%
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