SAFER: Stuck-At-Fault Error Recovery for Memories

Seong, Nak Hee; Woo, Dong Hyuk; Srinivasan, Vijayalakshmi; Rivers, Jude A.; Lee, Hsien-Hsin S.

doi:10.1109/micro.2010.46

Cited by 172 publications

(127 citation statements)

References 18 publications

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“…Prior work has also considered low-overhead techniques for hiding failures in memories that experience wear-out [11,34,39,40]. Our failed-block recycling technique extends this prior work by selectively relaxing error correction on memory that contains approximate data.…”

Section: Related Workmentioning

confidence: 96%

“…Thus, techniques for hiding failures from software are critical to providing a useful lifespan for a memory [21]. These techniques typically abandon portions of memory containing uncorrectable failures and use only failure-free blocks [34,39,40]. By employing otherwise-unusable failed blocks to store approximate data, it is possible to extend the lifetime of an array as long as sufficient intact capacity remains to store the application's precise data.…”

Section: Using Failed Memory Cellsmentioning

confidence: 99%

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Approximate Storage in Solid-State Memories

Sampson

Nelson

Strauß

et al. 2014

ACM Trans. Comput. Syst.

126

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Memories today expose an all-or-nothing correctness model that incurs significant costs in performance, energy, area, and design complexity. But not all applications need high-precision storage for all of their data structures all of the time. This paper proposes mechanisms that enable applications to store data approximately and shows that doing so can improve the performance, lifetime, or density of solid-state memories. We propose two mechanisms. The first allows errors in multi-level cells by reducing the number of programming pulses used to write them. The second mechanism mitigates wear-out failures and extends memory endurance by mapping approximate data onto blocks that have exhausted their hardware error correction resources. Simulations show that reduced-precision writes in multi-level phase-change memory cells can be 1.7× faster on average and using failed blocks can improve array lifetime by 23% on average with quality loss under 10%.

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Section: Related Workmentioning

confidence: 96%

Section: Using Failed Memory Cellsmentioning

confidence: 99%

Approximate Storage in Solid-State Memories

Sampson

Nelson

Strauß

et al. 2014

ACM Trans. Comput. Syst.

126

View full text Add to dashboard Cite

show abstract

“…Hardware-only error correction replaces bits or entire lines on permanent failures [16,22,23,25]. These papers assume that once the finite error correction resources are exhausted, the entire page, if not the entire memory, fails.…”

Section: Pcm Hardwarementioning

confidence: 99%

“…When one line in DRAM fails, software remaps its virtual page to another working physical page and discards the entire failed physical page [9]. Even recent work on error correction hardware tailored to wearable memories [16,22,23,25] assumes that once the finite error correction resources are exhausted, the entire page, if not the entire memory, fails. Assuming only pages fail, 4 KB pages and 64 B lines, this solution wastes 98% of working memory.…”

Section: Introductionmentioning

confidence: 99%

Using managed runtime systems to tolerate holes in wearable memories

et al. 2013

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New memory technologies, such as phase-change memory (PCM), promise denser and cheaper main memory, and are expected to displace DRAM. However, many of them experience permanent failures far more quickly than DRAM. DRAM mechanisms that handle permanent failures rely on very low failure rates and, if directly applied to PCM, are extremely inefficient: Discarding a page when the first line fails wastes 98% of the memory. This paper proposes low complexity cooperative software and hardware that handle failure rates as high as 50%. Our approach makes error handling transparent to the application by using the memory abstraction offered by managed languages. Once hardware error correction for a memory line is exhausted, rather than discarding the entire page, the hardware communicates the failed line to a failure-aware OS and runtime. The runtime ensures memory allocations never use failed lines and moves data when lines fail during program execution. This paper describes minimal extensions to an Immix mark-region garbage collector, which correctly utilizes pages with failed physical lines by skipping over failures. This paper also proposes hardware support that clusters failed lines at one end of a memory region to reduce fragmentation and improve performance under failures. Contrary to accepted hardware wisdom that advocates for wear-leveling, we show that with software support non-uniform failures delay the impact of memory failure. Together, these mechanisms incur no performance overhead when there are no failures and at failure levels of 10% to 50% suffer only an average overhead of 4% and 12%, respectively. These results indicate that hardware and software cooperation can greatly extend the life of wearable memories.

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“…Most authors assume endurance of 10 8 write cycles, but recently developed fully-confined PCRAM cells have much longer lifetime (more than 10 11 write cycles) [7]. We can also combine wear-leveling [20], failure tolerance [23,29,24,16] and write buffers (SRAM or DRAM) to cope with write endurance.…”

Section: Limitations and Future Workmentioning

confidence: 99%

Exploring latency-power tradeoffs in deep nonvolatile memory hierarchies

Yoon

Gonzalez

Ranganathan

et al. 2012

Proceedings of the 9th Conference on Computing Frontiers

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To handle the demand for very large main memory, we are likely to use nonvolatile memory (NVM) as main memory. NVM main memory will have higher latency than DRAM. To cope with this, we advocate a less-deep cache hierarchy based on a large last-level, NVM cache. We develop a model that estimates average memory access time and power of a cache hierarchy. The model is based on captured application behavior, an analytical power and performance model, and circuit-level memory models such as CACTI and NVSim. We use the model to explore the cache hierarchy design space and present latency-power tradeoffs for memory intensive SPEC benchmarks and scientific applications. The results indicate that a flattened hierarchy lowers power and improves average memory access time.

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SAFER: Stuck-At-Fault Error Recovery for Memories

Cited by 172 publications

References 18 publications

Approximate Storage in Solid-State Memories

Approximate Storage in Solid-State Memories

Using managed runtime systems to tolerate holes in wearable memories

Exploring latency-power tradeoffs in deep nonvolatile memory hierarchies

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