SAD-Based Stereo Matching Circuit for FPGAs

Perri, Stefania; Colonna, D.; Zicari, Paolo; Corsonello, Pasquale

doi:10.1109/icecs.2006.379921

Cited by 33 publications

(20 citation statements)

References 2 publications

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“…They used a Xilinx Virtex II FPGA, processing three 320 Â 240 camera images with block size 15 Â 15 and a disparity range of 32 pixels, achieving 100 fps. Perri et al [21] proposed an FPGA-based stereo matching circuit processing 512 Â 512 images, using block size 5 Â 5 for the SAD and a disparity range of 255 pixels at a frame rate of 25.6 fps.…”

Section: Related Workmentioning

confidence: 99%

Accurate hardware-based stereo vision

Ambrosch¹,

Kubinger²

2010

Computer Vision and Image Understanding

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Section: Related Workmentioning

confidence: 99%

Accurate hardware-based stereo vision

Ambrosch¹,

Kubinger²

2010

Computer Vision and Image Understanding

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“…The system can process images with a size of 270 × 270 at a frame rate of 30 fps. Paper [4] presents a FPGA-based stereo matching system that operates on 512 × 512 stereo images with a maximum disparity of 255 and achieves a frame rate of 25.6 fps running under a frequency of 286 MHz. In [5], a development system based on four Xilinx XCV2000E chips is used to implement a dense, phase correlation-based stereo system that runs at a frame rate of 30 fps for 256 × 360 pixels stereo pairs.…”

Section: Introductionmentioning

confidence: 99%

SAD-Based Stereo Vision Machine on a System-on-Programmable-Chip (SoPC)

Zhang

Chen

2013

Sensors

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This paper, proposes a novel solution for a stereo vision machine based on the System-on-Programmable-Chip (SoPC) architecture. The SOPC technology provides great convenience for accessing many hardware devices such as DDRII, SSRAM, Flash, etc., by IP reuse. The system hardware is implemented in a single FPGA chip involving a 32-bit Nios II microprocessor, which is a configurable soft IP core in charge of managing the image buffer and users' configuration data. The Sum of Absolute Differences (SAD) algorithm is used for dense disparity map computation. The circuits of the algorithmic module are modeled by the Matlab-based DSP Builder. With a set of configuration interfaces, the machine can process many different sizes of stereo pair images. The maximum image size is up to 512 K pixels. This machine is designed to focus on real time stereo vision applications. The stereo vision machine offers good performance and high efficiency in real time. Considering a hardware FPGA clock of 90 MHz, 23 frames of 640 × 480 disparity maps can be obtained in one second with 5 × 5 matching window and maximum 64 disparity pixels.

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“…However, the depth-map algorithm is computational and data intensive [2] because it has to perform an identical procedure on millions of pixel. Due to the computational complexity of the disparity algorithms, several attempts have been made [3][4][5], including systems implemented on personal computer, digital signal processor (DSP), field programmable gate array (FPGA) and application specific integrated circuit (ASIC).…”

Section: Introductionmentioning

confidence: 99%

Resource minimization in a real-time depth-map processing system on FPGA

Tan

Hamid

Sebastian

et al. 2011

TENCON 2011 - 2011 IEEE Region 10 Conference

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Depth-map algorithm allows camera system to estimate depth. It is a computational intensive algorithm, but can be implemented with high speed on hardware due to the parallelism property. When depth-map algorithm is implemented on FPGA, resource consumption is one of the issues. The problem is normally resolved by modifying the algorithm, but the problem can also be solved by implementing new hardware architectures without modification of the depthmap algorithm. This work implemented five different processor architectures for the sum of absolute difference (SAD) depth-map algorithm on FPGA in real-time. Resource usage and performance of these architectures were compared. Memory contention and bandwidth constraints were resolved by using self-initiative memory controller, FIFOs and line buffers. Parallel processing was utilized to achieve high processing speed at low clock frequency. Memory-based line buffers were used instead of register-based line buffers to save 62.4% of logic elements (LEs) used. Usage of registers to replace repetitive subtractors saves 24.75% of LEs. The system achieves performance of 295 mega pixel disparity per second(MPDS) for the architecture with 640x480 pixels image, 3x3 pixels window size, 32 pixels disparity range and 30 frames per second. It achieves processing speed of 590 MPDS for the 64 pixels disparity range architecture. The disparity matching module works at the frequency of 10 MHz and produces one pixel of result every clock cycle.

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SAD-Based Stereo Matching Circuit for FPGAs

Cited by 33 publications

References 2 publications

Accurate hardware-based stereo vision

Accurate hardware-based stereo vision

SAD-Based Stereo Vision Machine on a System-on-Programmable-Chip (SoPC)

Resource minimization in a real-time depth-map processing system on FPGA

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