Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control

Bian, Song; Shintani, Michihiro; Wang, Zheng; Hiromoto, Masayuki; Chattopadhyay, Anupam; Satō, Takashi

doi:10.1109/ats.2016.31

Cited by 8 publications

(8 citation statements)

References 12 publications

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“…Equation (8) shows that I sub is dependent on the V th of the transistor, and the V th increase induced by the NBTI effect can decrease the leakage current for the gate. The leakage power change induced by NBTI over time is not considered in this paper, and we extract the leakage power for each gate with all possible input vectors at the starting time of the circuit, which is the maximum value.…”

Section: Cell-based Leakage Power Modelmentioning

confidence: 99%

NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method

Sun

Yang

et al. 2017

Algorithms

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As technology scales, negative bias temperature instability (NBTI) becomes one of the primary failure mechanisms for Very Large Scale Integration (VLSI) circuits. Meanwhile, the leakage power increases dramatically as the supply/threshold voltage continues to scale down. These two issues pose severe reliability problems for complementary metal oxide semiconductor (CMOS) devices. Because both the NBTI and leakage are dependent on the input vector of the circuit, we present an input vector control (IVC) method based on a linear programming algorithm, which can co-optimize circuit aging and power dissipation simultaneously. In addition, our proposed IVC method is combined with the supply voltage assignment technique to further reduce delay degradation and leakage power. Experimental results on various circuits show the effectiveness of the proposed combination method.

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Section: Cell-based Leakage Power Modelmentioning

confidence: 99%

NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method

Sun

Yang

et al. 2017

Algorithms

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“…In [4]- [6], the stress probability is reduced by forcing the gate input to be logical "1." In these papers, the selected logic gates in a circuit are replaced with INC logics so that the input signal probability of the downstream logic gates is controlled.…”

Section: Mitigation Of Circuit Degradation By Inc Logicmentioning

confidence: 99%

“…By asserting the recovery signal, the signal probability of the direct downstream gates decreases and the degradation is mitigated. In [6], stress gates are estimated in advance, and those gates are replaced to INC logics.…”

Section: Mitigation Of Circuit Degradation By Inc Logicmentioning

confidence: 99%

“…There are intensive studies in the field related to NBTI degradation [2]- [6]. The NBTI degradation is related to the average frequency of stress phase (signal probability).…”

Section: Introductionmentioning

confidence: 99%

“…In order to avoid losing logic states, these techniques need to be applied when the circuit is in a sleep mode. In contrast with these, a technique that practices NBTI mitigation when no operation (NOP) instruction is brought out is proposed in [6]. This enables the mitigation of NBTI even when the processor is working.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation

Morita

Bian

Shintani

et al. 2017

IEICE Trans. Fundamentals

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Replacement of highly stressed logic gates with internal node control (INC) logics is known to be an effective way to alleviate timing degradation due to NBTI. We propose a path clustering approach to accelerate finding effective replacement gates. Upon the observation that there exist paths that always become timing critical after aging, critical path candidates are clustered to select representative path in each cluster. With efficient data structure to further reduce timing calculation, INC logic optimization has first became tractable in practical time. Through the experiments using a processor, 171x speedup has been demonstrated while retaining almost the same level of mitigation gain.

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NBTI and Power Reduction Using a Workload-Aware Supply Voltage Assignment Approach

Liang

Yang

et al. 2018

J Electron Test

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Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control

Cited by 8 publications

References 12 publications

NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method

NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method

Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation

NBTI and Power Reduction Using a Workload-Aware Supply Voltage Assignment Approach

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