Runtime FPGA partial reconfiguration

McDonald, Eric

doi:10.1109/maes.2008.4579286

Cited by 19 publications

(20 citation statements)

References 5 publications

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“…To implement a partial reconfiguration design successfully, up-front planning is essential [14]. Designer needs to identify which functions can be swapped in real time and which functions need to remain running.…”

Section: Partial Reconfiguration Methodologymentioning

confidence: 99%

“…Bus macros are physical ports which connect a partial reconfigurable module (PRM) to static logic [1,9]. Any connection from a PRM to static logic should always go through a bus macro [1,14]. Figure 2 shows the physical implementation of a bus macro.…”

Section: Fig 2 Xilinx Bus Macrosmentioning

confidence: 99%

“…Reconfiguration speed is another factor while designing with partial configuration. Reconfiguration speed depends on the bit stream size [14]. Large reconfiguration overhead is involved, while accessing the data from external memory.…”

Section: Reconfigurable Fft Designmentioning

confidence: 99%

“…The frames are composed of many 32-bit words. The smallest Virtex-II device, the XC2VP2, has 884 frames, and the largest device, theXC2VP100, has 3,500 frames [14]. The metric of µsec/Frame is used when calculating the reconfiguration speed.…”

Section: Reconfigurable Fft Designmentioning

confidence: 99%

“…The so-called DPR can be exploited in many application fields, for instance, to fulfill space requirements in small portable systems, to create a system-on-a-chip with a very high level of flexibility, and to realize adaptive hardware algorithms. The Xilinx FPGAs (i.e., Virtex series) are some of a few devices on the market allowing DPR [2,5,12,14].…”

Section: Introductionmentioning

confidence: 99%

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Dynamic Partial Reconfigurable FFT for OFDM Based Communication Systems

Vennila

Lakshminarayanan

2011

Circuits Syst Signal Process

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This paper presents a novel scalable and runtime dynamically reconfigurable FFT architecture for different wireless standards. With only 8 butterfly units, a reconfigurable FFT architecture for three different FFT points is realized using mixed radix-2 2 /2 3 /2 4 FFT algorithm in a modified Single-path Delay Feedback (SDF) pipelined architecture. Via a proper data flow reconfiguration it can support 64, 128 and 256. It can even be extended up to 8192-point transforms and uses only 13 butterfly units to realize 8192 points. This paper describes the implementation method of 256 and 128 point FFT, which is reconfigured partially from 64 point FFT. The whole system is implemented on a Xilinx XC2VP30 FPGA device. The implementation design addresses area efficiency and flexibility allowing the insertion of the partial modules dynamically to realize various FFT sizes. To verify the efficacy of this dynamic partial reconfigurable FFT design method, a conventional multiplexer based reconfigurable architecture was designed and tested on the same platform. Tested FPGA results for the Dynamic Partial Reconfigurable (DPR) method show the configuration time improvement and good area efficiency as compared to the reconfigurable architecture using conventional multiplexer techniques.

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Section: Partial Reconfiguration Methodologymentioning

confidence: 99%

Section: Fig 2 Xilinx Bus Macrosmentioning

confidence: 99%

Section: Reconfigurable Fft Designmentioning

confidence: 99%

Section: Reconfigurable Fft Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Dynamic Partial Reconfigurable FFT for OFDM Based Communication Systems

Vennila

Lakshminarayanan

2011

Circuits Syst Signal Process

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Dynamic reconfiguration in FPAA for technical and nontechnical education in a global environment

Macho

Teruel

García-Loro

et al. 2020

Comp Applic In Engineering

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Some engineering concepts have been proven to be very important not only in engineering degrees but in several areas. This knowledge is difficult to grasp under certain circumstances, and sometimes prior training is needed. This is a special challenge in full or part remote education. Simulations may help in this area, but truly experimental lab practices are crucial to grasp all the required knowledge and not only for fundamental information but for complex or indirect knowledge, where students can apply what they have learnt in classes.In this paper, we have worked on a concept to help professors and students to get new concepts in a more time-efficient and safe manner, using dynamic reconfiguration in Field-Programmable Analog Array. This solution can be easily applied to traditional or remote labs in less time than usual practices, so students can learn more in the same amount of time, especially when time is a constraint.

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Algorithms for reducing reconfiguration overheads using prefetch, reuse, and optimal mapping of tasks

Hariharan

Kannan

2018

Concurrency and Computation

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Summary Field Programmable Gate Arrays (FPGAs) are preferred in the modern embedded system to accelerate the performance of the entire system. However, the FPGAs are liable to suffer from reconfiguration overheads. These overheads are mainly because of the configuration data being fetched from the off‐chip memory at run‐time and due to the improper management of tasks during execution. To reduce these overheads, two algorithms are proposed. Both the algorithms focus on the prefetch heuristics, reuse technique, and an optimal mapping of tasks over the available memories. However, in terms of reusing technique, algorithm‐1 uses least recently used (LRU) policy and algorithm‐2 uses the optimal replacement policy (considering the vitality of the reconfigurable units (RUs)). Simulation results are obtained for both the algorithms. It is evident from the result that most of the reconfiguration overheads are eliminated when the applications are managed and executed based on the proposed algorithms. Also, the two algorithm results are compared and analyzed. For this purpose, the experiments included smaller and larger task graphs. In the case of smaller task graphs, algorithm‐2 outperforms algorithm‐1 in reducing reconfiguration overheads. In larger task graphs, algorithm‐1 produces better results compared to algorithm‐2.

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Runtime FPGA partial reconfiguration

Cited by 19 publications

References 5 publications

Dynamic Partial Reconfigurable FFT for OFDM Based Communication Systems

Dynamic Partial Reconfigurable FFT for OFDM Based Communication Systems

Dynamic reconfiguration in FPAA for technical and nontechnical education in a global environment

Algorithms for reducing reconfiguration overheads using prefetch, reuse, and optimal mapping of tasks

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