Runahead execution vs. conventional data prefetching in the IBM POWER6 microprocessor

Cain, Harold W.; Nagpurkar, Priya

doi:10.1109/ispass.2010.5452021

Cited by 9 publications

(5 citation statements)

References 40 publications

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“…Cain et al studied prefetchers on IBM Power architectures [5]. New designs are proposed to address the over-aggressiveness of current prefetchers [10,11,15].…”

Section: Performance Resultsmentioning

confidence: 99%

Performance analysis of thread mappings with a holistic view of the hardware resources

Wang

Dey

Mars

et al. 2012

2012 IEEE International Symposium on Performance Analysis of Systems &Amp; Software

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With the shift to chip multiprocessors, managing shared resources has become a critical issue in realizing their full potential. Previous research has shown that thread mapping is a powerful tool for resource management. However, the difficulty of simultaneously managing multiple hardware resources and the varying nature of the workloads have impeded the efficiency of thread mapping algorithms. To overcome the difficulties of simultaneously managing multiple resources with thread mapping, the interaction between various microarchitectural resources and thread characteristics must be well understood.This paper presents an in-depth analysis of PARSEC benchmarks running under different thread mappings to investigate the interaction of various thread mappings with microarchitectural resources including, L1 I/D-caches, I/D TLBs, L2 caches, hardware prefetchers, off-chip memory interconnects, branch predictors, memory disambiguation units and the cores. For each resource, the analysis provides guidelines for how to improve its utilization when mapping threads with different characteristics. We also analyze how the relative importance of the resources varies depending on the workloads. Our experiments show that when only memory resources are considered, thread mapping improves an application's performance by as much as 14% over the default Linux scheduler. In contrast, when both memory and processor resources are considered the mapping algorithm achieves performance improvements by as much as 28%. Additionally, we demonstrate that thread mapping should consider L2 caches, prefetchers and off-chip memory interconnects as one resource, and we present a new metric called L2-misses-memory-latency-product (L2MP) for evaluating their aggregated performance impact.

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“…Cain et al studied prefetchers on IBM Power architectures [5]. New designs are proposed to address the over-aggressiveness of current prefetchers [10,11,15].…”

Section: Performance Resultsmentioning

confidence: 99%

Performance analysis of thread mappings with a holistic view of the hardware resources

Wang

Dey

Mars

et al. 2012

2012 IEEE International Symposium on Performance Analysis of Systems &Amp; Software

View full text Add to dashboard Cite

show abstract

“…And sometimes the technique is intended for certain targeted applications such as excessively memory-bound programs. A fully automated mechanism to make these decisions may have difficulty achieving effectiveness reported in literature [10], especially when targeting a broad spectrum of applications. ii) A contributing factor to the manual approach is the notion of "delinquent instructions": a few culprits created most of the performance problems.…”

Section: Background and Related Workmentioning

confidence: 99%

R3-DLA (Reduce, Reuse, Recycle): A More Efficient Approach to Decoupled Look-Ahead Architectures

Kondguli

Huang

2019

2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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Modern societies have developed insatiable demands for more computation capabilities. Exploiting implicit parallelism to provide automatic performance improvement remains a central goal in engineering future general-purpose computing systems. One approach is to use a separate thread context to perform continuous look-ahead to improve the data and instruction supply to the main pipeline. Such a decoupled look-ahead (DLA) architecture can be quite effective in accelerating a broad range of applications in a relatively straightforward implementation. It also has broad design flexibility as the look-ahead agent need not be concerned with correctness constraints. In this paper, we explore a number of optimizations that make the look-ahead agent more efficient and yet extract more utility from it. With these optimizations, a DLA architecture can achieve an average speedup of 1.4 over a state-of-the-art microarchitecture for a broad set of benchmark suites, making it a powerful tool to enhance single-thread performance.

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“…MLP), in the successor blocks that we can hoist (a function of ALPBB, PDIH and PHI). • tendency to stall at branch resolution (ASPCB) • modest L1 D$ miss rate as we do not employ Runahead [10,4] or iCFP [19] • good I$ performance…”

Section: Experimental Evaluationmentioning

confidence: 99%

Branch vanguard

McFarlin

Zilles

2015

Proceedings of the 42nd Annual International Symposium on Computer Architecture

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While control speculation is highly effective for generating good schedules in out-of-order processors, it is less effective for in-order processors because compilers have trouble scheduling in the presence of unbiased branches, even when those branches are highly predictable. In this paper, we demonstrate a novel architectural branch decomposition that separates the prediction and deconvergence point of a branch from its resolution, which enables the compiler to profitably schedule across predictable, but unbiased branches. We show that the hardware support for this branch architecture is a trivial extension of existing systems and describe a simple code transformation for exploiting this architectural support. As architectural changes are required, this technique is most compelling for a dynamic binary translation-based system like Project Denver.We evaluate the performance improvements enabled by this transformation for several in-order configurations across the SPEC 2006 benchmark suites. We show that our technique produces a Geomean speedup of 11% for SPEC 2006 Integer, with speedups as large as 35%. As floating point benchmarks contain fewer unbiased, but predictable branches, our Geomean speedup on SPEC 2006 FP is 7%, with a maximum speedup of 26%.

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Runahead execution vs. conventional data prefetching in the IBM POWER6 microprocessor

Cited by 9 publications

References 40 publications

Performance analysis of thread mappings with a holistic view of the hardware resources

Performance analysis of thread mappings with a holistic view of the hardware resources

R3-DLA (Reduce, Reuse, Recycle): A More Efficient Approach to Decoupled Look-Ahead Architectures

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