Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC and SVC Video Codecs

Otero, Andrés; Cervero, T.; Torre, Eduardo de la; López, Sebastián; Callicó, Gustavo M.; Riesgo, Teresa; Sarmiento, Roberto

doi:10.1007/978-1-4614-1362-2_8

Cited by 3 publications

(2 citation statements)

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“…Furthermore, due to its regular and systolic properties, it has been implemented using the tile-based run-time assembly methodology explained previously. More details can be found in [10].…”

Section: A First Player: Deblocking Filtermentioning

confidence: 99%

Scalable Models for Autonomous Self-Assembled Reconfigurable Systems

Cervero

López

Sarmiento

et al. 2011

2011 International Conference on Reconfigurable Computing and FPGAs

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FPGAs are well-suited for applications that need to adjust the composition of computational structures over the lifetime of the application. While the underlying hardware framework for supporting run-time reconfiguration has existed for years, there have been negligibly few FPGA applications that have benefited from this. This is likely not an issue with FPGA architectures, yet it is more likely a formulation problem due to a highly restrictive model for reconfiguration provided by the vendors. This paper introduces a new paradigm in reconfigurable computing, where multiple designs may dynamically compete for resources in the same die. The way to afford this challenge is taking advantage of the benefits of the scalable and adaptable designs, since they achieve a balance between performance and flexibility. Thus, this paper proposes two alternative models for the assembly of computational structures that are conducive to autonomous self-assembled embedded systems, because of their high level of adaptability. To illustrate this new scenario, an example is examined that is based on two competing video image processing tasks.

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Section: A First Player: Deblocking Filtermentioning

confidence: 99%

Scalable Models for Autonomous Self-Assembled Reconfigurable Systems

Cervero

López

Sarmiento

et al. 2011

2011 International Conference on Reconfigurable Computing and FPGAs

View full text Add to dashboard Cite

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“…Swapping between variations of these architectures can be carried out by only reconfiguring the modules that differ, leaving the other common submodules unaltered. Variations may involve changing the size of the processing architecture at run-time, thus providing dynamic scalability [20]. It is essential to notice that the main difference between coarse and medium granularities is how the accelerator is composed, rather than the size of the RM.…”

Section: B Medium Granularitymentioning

confidence: 99%

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

et al. 2020

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Dynamic partial reconfiguration technique can be used to modify regions of an FPGA as large as the whole reconfigurable fabric or as small as individual logic elements. However, FPGA manufacturers have focused their efforts on designing tools that support the design of monolithic reconfigurable accelerators spanning large regions of the device. Nevertheless, in some applications, it is enough to fine-tune the accelerators' behavior instead of changing them entirely. In these cases, rather than allocating new accelerators, it is possible to reconfigure individual logic elements of the circuit, such as look-up tables or flip-flops. There is also an intermediate approach that targets the reconfigurability of accelerators composed of several tightly interconnected modules, such as overlays. In those architectures, it is possible to reconfigure only the modules that differ between the existing accelerator versions, thus reducing the reconfigurable footprint granularity. This paper proposes a classification of the approaches above, categorizing them as coarse, fine, and medium grain, respectively. There are neither commercial nor academic tools supporting multi-grain reconfiguration to take advantage of each granularity strength on commercial FPGAs. Differently, this paper proposes a tool called IMPRESS, that provides design-time and run-time support for multi-grain reconfiguration in Xilinx 7 Series FPGAs. Specific criteria are provided to combine the different granularity levels, trading off the benefits in terms of flexibility and performance, with different design and run-time costs. Two use cases in the image processing and neural network domains have been implemented to show how IMPRESS can build multi-grain reconfigurable systems.

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