Run-Time Exchange of Mechatronic Controllers Using Partial Hardware Reconfiguration

Danne, Klaus; Bobda, Christophe; Kalte, Heiko

doi:10.1007/978-3-540-45234-8_27

Cited by 17 publications

(7 citation statements)

References 6 publications

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“…The use of the dynamic partial reconfiguration is a very active research area. The "Hardware Plugins" concept makes sense with the new huge a partially reconfigurable capable FPGAs [12], [13]. In this approach the system is strongly unitized.…”

Section: Dynamic Partial Reconfiguration Conceptsmentioning

confidence: 99%

Implementation of a reconfigurable computing system for space applications

Cai

Zhao

Lan

2011

2011 International Conference on System Science, Engineering Design and Manufacturing Informatization

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high reliability is usually the most important requirement in space applications. There is no hardware repair for them. Long mission times and harsh environment are a challenge for electronic circuits, and particular error mitigation techniques have to be implemented in order to be able to cope with the expected error effects. Always, Triple Modular Redundancy (TMR) is relied mostly to prevent SEUs from causing functional errors. And in recent decades, SRAM based FPGAs are used a lot in space for its high performance and flexibility. However, use of FPGAs in space applications can also be challenging. They are too susceptible to transient faults, such as SEUs. Reconfiguration provides more possibilities for SRAM-based FPGAs into space. Reconfigurable technology solves the disadvantage that the TMR modules cannot heal the error themselves. Additionally, reconfiguration is an improvement in terms of resource utilization and costs. In this paper, TMR and reconfigurable computing are combined to level up the reliability of the space applications. The paper proposed a reconfigurable computing architecture based on a TMR system. A new kind of reconfigurable architecture using SoP (system-on-a-package)technology is presented. Also, a whole space application will be presented.

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Section: Dynamic Partial Reconfiguration Conceptsmentioning

confidence: 99%

Implementation of a reconfigurable computing system for space applications

Cai

Zhao

Lan

2011

2011 International Conference on System Science, Engineering Design and Manufacturing Informatization

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“…Despite an increasing number of modern FPGAs providing partial run-time reconfiguration-two core requirements for dynamic reconfiguration-methods that allow to exploit these additional flexibilities are rarely found. Nevertheless, some work has been done that proofs the benefit of fine grain granularity and high adaptability of FPGAs, e. g. in [3,4,5,6,7,8].…”

Section: Introductionmentioning

confidence: 99%

Algorithmic Skeletons for the Programming of Reconfigurable Systems

Dittmann

2007

Software Technologies for Embedded and Ubiquitous Systems

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Abstract. Reconfigurable hardware such as FPGAs combines performance and flexibility, two inherent requirements of many modern electronic devices. Moreover, using reconfigurable devices, time to market can be reduced while simultaneously cutting the costs. However, the design of systems that beneficially explore the reconfiguration capabilities of modern FPGAs is cumbersome and little automated. In this work, a new approach is described that starts from a very high level of abstraction, so-called algorithmic skeletons, and exploits the additional information of this level of abstraction to beneficially execute on reconfigurable devices. Particularly, the approach focuses on dynamic run-time reconfiguration on partially reconfigurable FPGAs. As a first introduction to this approach, we consider stream parallelism paradigms including their composition.

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“…In [1] we introduced an FPGA implementation of a multi-controller which uses the runtime reconfiguration feature of FPGAs to interchange the controller modules during runtime. Here we investigate a more abstract view of the system.…”

Section: Multi-controllermentioning

confidence: 99%

Dynamic reconfiguration of distributed arithmetic controllers: design space exploration and trade-off analysis

Danne

Bobda²

18th International Parallel and Distributed Processing Symposium, 2004. Proceedings.

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This work explores various solutions to implement an application using runtime reconfigurable field programmable gate arrays (FPGA). The example is a mechatronic control system which has to adapt its behavior from time to time. Our model is a task-graph where every task is associated with an hardware module characterized by its required FPGA resource and its execution time. We propose various mappings of the tasks onto the FPGA. For the implementation of the tasks themselves the computation technique known as distributed arithmetic is used. We achieve numerous alternatives with different resource consumptions and execution times for every task. We estimate these characteristics and compare them to synthesis results. The received values are used to get the characteristics of the over-all system. The results show that the optimal mapping depends on the application timing constrains, on the complexity of the tasks as well as on the reconfiguration speed of the used FPGA. 1

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Run-Time Exchange of Mechatronic Controllers Using Partial Hardware Reconfiguration

Cited by 17 publications

References 6 publications

Implementation of a reconfigurable computing system for space applications

Implementation of a reconfigurable computing system for space applications

Algorithmic Skeletons for the Programming of Reconfigurable Systems

Dynamic reconfiguration of distributed arithmetic controllers: design space exploration and trade-off analysis

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