Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)

DOI: 10.1109/fpt.2004.1393302

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RTOS acceleration on soft-core processors using instruction set customization

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M. Sindhwani²,

Thambipillai Srikanthan³

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Cited by 5 publications

References 10 publications

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Architecture, performance modeling and VLSI implementation methodologies for ASIC vector processors: A case study in telephony workloads

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et al. 2013

Microprocessors and Microsystems

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Architecture, performance modeling and VLSI implementation methodologies for ASIC vector processors: A case study in telephony workloads

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²

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et al. 2013

Microprocessors and Microsystems

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Framework for Automated Application-Specific Optimization of Embedded Real-Time Operating Systems

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2005 5th International Conference on Information Communications &Amp; Signal Processing

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In recent years, embedded systems have become increasingly more complex. This complexity is tackled in software by abstracting the underlying hardware using an embedded real-time operating system (RTOS) and a suitable Board Support Package (BSP). However, the RTOS imposes overheads on the CPU in return for the run-time support it provides. Modern embedded hardware often comprises multicore processors, unified core processors, soft-core processors, dedicated hardware logic, or even a system-on-chip. Each of these hardware options can be used to reduce the CPU overhead of the RTOS and numerous methods have been proposed in literature. Due to the large number of optimization options available and the need to meet strict time-to-market pressures, RTOS optimization needs to be a largely autonomous process. In this paper, we present a framework for automated applicationspecific optimization of embedded real-time operating systems. We identify the components of such a framework and discuss our prototype of the framework.

A FPGA based C runtime hardware accelerator

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²

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et al. 2011

2011 9th IEEE International Conference on Industrial Informatics

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