RSVP II: a next generation automotive vector processor

Chiricescu, Silviu; Chai, Sek; Moat, K.; Lucas, B. W.; May, P.; Norm, J.; Essick, R.; Schuette, Michael A.

doi:10.1109/ivs.2005.1505163

Cited by 9 publications

(3 citation statements)

References 2 publications

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“…only one adder, one port per input stream, etc. ), c 3 corresponds to a very wide configuration with a large number of functional units and c 2 corresponds to an intermediate configuration, which is the same as the RSVP™-II implementation [4]. The u i parameters show the degree of unrolling of the sDFG to achieve higher throughput.…”

Section: Table 2 Speed Up Of the Lpr Application And Kernelsmentioning

confidence: 99%

FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators

Bellas

Chai

Dwyer

et al. 2006

Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium

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Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based System on Chip (SoC) that meet the applications requirements. The designer can customize the hardware by selecting from a large number of pre-defined peripherals and fixed IP functions and by providing new hardware, typically expressed using RTL. Hardware accelerators that provide application-specific extensions to the computational capabilities of a system is an efficient mechanism to enhance the performance and reduce the power dissipation. What is missing is an integrated approach to identify the computationally critical parts of the application and to create accelerators starting from a high level representation with a minimal design effort.In this paper, we present an automation methodology and a tool that generates accelerators. We apply the methodology on an FPGA-based license plate recognition (LPR) system used in law enforcement. The accelerators process streaming data and support a programming model which can naturally express a large number of embedded applications resulting in efficient hardware implementations. We show that we can achieve an overall LPR application speed up from 1.2x to 2.6x, thus enabling real-time functionality under realistic road scenes.

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Section: Table 2 Speed Up Of the Lpr Application And Kernelsmentioning

confidence: 99%

FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators

Bellas

Chai

Dwyer

et al. 2006

Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium

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“…Reconfigurable logic is an effective medium for creating pipelined hardware as well as for exploiting parallelism. The Reconfigurable Streaming Vector Processor (RSVP™ II 1 ) [1,2] is a pipelined vector coprocessor architecture that has been implemented on reconfigurable fabric targeting multimedia applications. Such streaming accelerators employ a set of functional units (FU) and they utilize functional pipelining heavily where it is essential to register the inputs and outputs of FUs.…”

Section: Introductionmentioning

confidence: 99%

Pre-Synthesis Area Estimation of Reconfigurable Streaming Accelerators

Mondal

Memik

Bellas

2006

2006 International Conference on Field Programmable Logic and Applications

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One of the major challenges in automated synthesis of reconfigurable accelerators is to create efficient designs that conform to the resource capacity of the target device. This work concerns estimation of the hardware cost before actually attempting the synthesis of streaming accelerators on reconfigurable platforms. Specifically, our proposed framework tackles the problem of pre-synthesis estimation of data queuing cost, while incorporating the potential impact of resource constraints on the final implementation. We present a probabilistic push-and-pull approach for register queue size estimation of a streaming data flow graph. We evaluated our techniques using an industrial toolflow. For the register queue sizes our estimations are within the range of -14.4% to 12.4% on an average, for various resource constraints on a set of multimedia applications.

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“…Therefore, register queues at the outputs of FUs is one of the major building blocks that enable communication between FUs. The Reconfigurable Streaming Vector Processor (RSVP™ II 1 ) [1,2] is such a highly pipelined vector coprocessor architecture that has been implemented on reconfigurable fabric with a limited set of links (which implement the FIFO register queues). Hence, it is imperative to incorporate these register queues in area estimation.…”

Section: Introductionmentioning

confidence: 99%