Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model

Huang, Yu-Hung; Xie, Zhiyao; Fang, Guan-Qi; Yu, Tao-Chun; Ren, Haoxing; Fang, Shao-Yun; Chen, Yiran; Hu, Jiang

doi:10.23919/date.2019.8715126

Cited by 30 publications

(15 citation statements)

References 22 publications

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“…Therefore, the target technology directly contains the macro blocks which can be directly utilized for. 2) Macro Placement: After the design has been mapped to the target technology, the macros have to be placed on the layout [5], [2], [6]. To this end, the placement underlies cost functions like minimizing the needed die area.…”

Section: A System-on-chip Physical Designmentioning

confidence: 99%

“…4) Sign-Off State: After placement and routing has been successfully performed, the defined constraints are finally checked again before the design can be exported and sent to the fabrication site [5].…”

Section: A System-on-chip Physical Designmentioning

confidence: 99%

“…Macro placement for SoC design has already been studied widely within the industrial as well as the academic research communities. These efforts led to multiple approaches including the application of meta-heuristic algorithms like Simulated Annealing (SA) [1], approaches based on Machine Learning (ML) [5], as well as Genetic Algorithms (GA) [2], or approaches based on reasoning engines [6], [9].…”

Section: B State Of the Art Macro Placementmentioning

confidence: 99%

“…However, heuristic-based approaches are not capable to guarantee that the macro placement which is based on an optimal die area is found. Recently, also approaches based on ML have been published for macro placement [5]. Compared to approaches based on SA or GA, ML as applied in [5] is used in order to support the placement algorithm (e.g.…”

Section: B State Of the Art Macro Placementmentioning

confidence: 99%

“…Recently, also approaches based on ML have been published for macro placement [5]. Compared to approaches based on SA or GA, ML as applied in [5] is used in order to support the placement algorithm (e.g. as cost function).…”

Section: B State Of the Art Macro Placementmentioning

confidence: 99%

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SMT-Based Placement for System-on-Chip Design

Pointner

Wenzek

Wille

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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The utilization of System on Chips (SoCs) for shortliving consumer applications has become very popular over the last decades. Because of that, more and more effort has been put into the physical design of SoCs and especially into the so-called macro placement step in order to keep the final price suitable for mass production. How to guarantee that the SoC is realized based on a minimal die area remains a challenging task. Current state-of-the-art solutions for this macro placement-problem mostly try to tackle the problem based on meta-heuristic-and genetic algorithms. However, although such methods are commonly used for macro placement, they can not guarantee that the macro placement and, therefore the die size is optimal. In this work, we are proposing the utilization of modern satisfiability solvers in order to generate optimized macro placements. To this end, we symbolically formulate the placement problem and forward it to a solver which allows us to obtain optimized solutions for the macro placement problem. In case this is not possible, search space pruning is employed which does not allow to employ the full optimization strategy anymore but still determines feasible results. We demonstrate the approach in experiments and made the resulting tool available as open-source.

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Section: A System-on-chip Physical Designmentioning

confidence: 99%

Section: A System-on-chip Physical Designmentioning

confidence: 99%

Section: B State Of the Art Macro Placementmentioning

confidence: 99%

Section: B State Of the Art Macro Placementmentioning

confidence: 99%

Section: B State Of the Art Macro Placementmentioning

confidence: 99%

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SMT-Based Placement for System-on-Chip Design

Pointner

Wenzek

Wille

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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P‐7: A High Resolution Design Methodology for Organic Photo Diode Sensor Integration

Kim,

Bang,

Yoo

et al. 2024

Symp Digest of Tech Papers

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In order for OPD to be integrated into the panel, high‐resolution design technology is required. The DSE makes various placements by changing the location and rotation of signal lines and devices, and makes optimal routing. We propose in order to reduce searching time and parasitic capacitance, the search priority is adjusted by high resolution predict models. In addition, a routing model is proposed to avoid congestion of routes and to search for a routing that minimizes overlapping areas between signal lines. Therefore, it is possible to find a layout that can reduce design areas by various placements and routes.

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