Round-robin arbiter design and generation

Abstract

In this paper, we introduce a Round-robin Arbiter Generator (RAG) tool. The RAG tool can generate a design for a Bus Arbiter (BA). The BA is able to handle the exact number of bus masters for both on-chip and off-chip buses. RAG can also generate a distributed and parallel hierarchical Switch Arbiter (SA). The first contribution of this paper is the automated generation of a round-robin token passing BA to reduce time spent on arbiter design. The generated arbiter is fair, fast, and has a low and predictable worst-case wait time. The second contribution of this paper is the design and integration of a distributed fast arbiter, e.g., for a terabit switch, based on 2x2 and 4x4 switch arbiters (SAs). Using a .25µ TSMC standard cell library from LEDA Systems [10,14], we show the arbitration time of a 256x256 SA for a terabit switch and demonstrate that the SA generated by RAG meets the time constraint to achieve approximately six terabits of throughput in a typical network switch design. Furthermore, our generated SA performs better than the Ping-Pong Arbiter and Programmable Priority Encoder by a factor of 1.9X and 2.4X, respectively.

Advance High Performance Bus Arbitration Techniques (AHB): A State-of-the-Art Review

“…This technology promises new levels of integration on a single chip, called the System-on-Chip (SoC) design, but also presents significant challenges to the chip designer. Processing cores on a single chip, may number well into the high ten's within the next decade, given the current rate of advancements [6] . Embedded systems design focuses on low Power dissipation and SoC.…”

Arbitrate-and-move primitives for high throughput on-chip interconnection networks

“…[4], [10], [13] and [18]). These works focused on n-to-1 arbitration, where a request vector ('1' means a request) of n-bits is given, and an n-bit grant vector is generated with only one granting signal among n bits.…”

“…In cases of crossbar network applications ( [4], [13] and [18]), the grant vector is used to configure the switches to connect input ports to output ports. Communication (moving data from input to output port) follows switch configuration.…”

“…N-bit arbiter circuits in each of [10], [13] and [18], were built in a tree structure, using 2-input or 4-input primitives. Critical delay path, which influences latency directly, extends from leaves to the root ( [10]) and in some cases, from leaves to the root and then back to leaves ( [13], [18]). [4] proposes a two-level design to reduce latency, which may work well for high number of inputs (n>2), however for 2-input arbiters a single level of logic gates would be sufficient.…”

“…[4] proposes a two-level design to reduce latency, which may work well for high number of inputs (n>2), however for 2-input arbiters a single level of logic gates would be sufficient. The arbiters, proposed in [4] and [13] are based on priority encoder circuits. Priority encoders are simpler and faster, compared to circuits in [10] and [18]; however, they require support of extra circuits to provide fairness among requesting inputs.…”