Rössler-based chaotic communication system implemented on FPGA

Schmitz, Jesse; Zhang, Lei

doi:10.1109/ccece.2017.7946729

Cited by 21 publications

(7 citation statements)

References 4 publications

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“…For instance, the PRNG proposed in [33], despite benefiting from its high dimensions and maximum frequency, still has a lower throughput than our generator, owing to the shorter length of its bitstream, which is only 60-bits (5× 12). Similarly, generators based on the forward-Euler method [32] and 3D Rössler's chaotic system [30] achieved throughputs of 4 Gbps and 2.85 Gbps, respectively. Another generator based on the 3D Nosé-Hoover chaotic system embedded in the Xilinx Kintex-7 FPGA achieved an output throughput of 2.03 Gbps [31], which is significantly lower than that of our CNN-HSG.…”

Section: Fpga Experimental Results and Comparisonmentioning

confidence: 99%

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FPGA implementation of orthogonal hyperchaotic sequences generator based on the CNN: application in multi-user chaotic communications

Fennouh,

Sadoudi,

Teguig

et al. 2023

Phys. Scr.

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In this article, we propose an efficient orthogonal hyperchaotic sequences generator for application in multi-user chaotic communication systems. The proposed generator consists of two blocks. The first block generates binary hyperchaotic sequences of varying lengths using a 6-Dimensional Cellular Neural Network (CNN) system, offering a wide range of sequence length choices. The second block uses an optimized selection method to generate multiple sets of orthogonal sequences with interesting correlation properties. The method is based on the balance and correlation properties, where zero cross-correlation between any two sequences is considered. A FPGA-based implementation of the proposed generator is presented. The hardware architecture is designed in VHDL and deployed on a Xilinx Virtex-6 FPGA ML605 evaluation kit. The generator is then analyzed and compared with the existing generator in terms of logic area consumption, throughput, latency, and randomness quality. The comparative analysis results show the effectiveness of the proposed generator, which can achieve a high throughput, low latency, and successfully pass all NIST statistical tests. Moreover, the generated orthogonal hyperchaotic sequences exhibit promising performance in a multi-user Differential Chaos Shift Keying (MU-DCSK) system, outperforming the Walsh-Hadamard sequences in terms of bit-error rate under various channel conditions.

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Section: Fpga Experimental Results and Comparisonmentioning

confidence: 99%

“…CriteriaProposed Bonny[32] Nguyen et al[33] Garg et al[31] Shmitz et al[30] Ismail et al[44] generator architecture, and the resulting sequences were stored in a text file.…”

mentioning

confidence: 99%

FPGA implementation of orthogonal hyperchaotic sequences generator based on the CNN: application in multi-user chaotic communications

Fennouh,

Sadoudi,

Teguig

et al. 2023

Phys. Scr.

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“…In the previous years, the chaos theory has played an important role in the design of the PRNGs, image hashing [60], and modulation schemes [61]. The Rössler [6] and Lorenz [7] are two of the most famous chaotic systems, and they have been utilized in a lot of encryption applications [8,9]. However, these two systems are based on multiplication operations that affect the hardware performance, regarding the area and speed.…”

Section: B Image Encryptionmentioning

confidence: 99%

On-the-Fly Parallel Processing IP-Core for Image Blur Detection, Compression, and Chaotic Encryption Based on FPGA

et al. 2021

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This paper presents a 3 in 1 standalone FPGA system which can perform color image blur detection in parallel with compression and encryption. Both blur detection and compression are based on the 3-level Haar wavelet transform, which is used as a common building block to save the resources. The compression is based on performing the hard thresholding scheme followed by the Run Length Encoding (RLE) technique. The encryption is based on the 128-bit Advanced Encryption Standard (AES), which is considered one of the most secure algorithms. Moreover, the modified Lorenz chaotic system is combined with the AES to perform the Cipher Block Chaining (CBC) mode. The proposed system is realized using HDL and implemented using Xilinx on XC5VLX50T FPGA. The system has utilized only 25% of the available slices. Furthermore, the system can achieve a throughput of 3.458 Gbps, which is suitable for realtime applications. To validate the compression performance, the system has been tested with all the standard 256×256 images. It is shown that depending on the amount of details in the image, the system can achieve 30dB PSNR at compression ratios in the range of (0.08-0.38). The proposed system can be integrated with digital cameras to process the captured images on-the-fly prior to transmission or storage. Based on the application, the blurred images can be either marked for future enhancement or simply filtered out.

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“…This implementation consumed 433 slices and 96 registers. In addition, this design utilized 12 DSP blocks to achieve 2850 Mbps of throughput [16]. Zhang has suggested yet another implementation of Lorenz attractor on Xilinx Spartan 3E and ZYNQ 7020 FPGAs which required 1029 and 338 slices respectively.…”

Section: Introductionmentioning

confidence: 99%

Attractor Influenced Prng for Cryptographic Key Generation on FPGA

Nalajala¹,

Rajesh²,

Sivaraman³

et al. 2019

First International Conference on Secure Reconfigurable Architectures &Amp; Intelligent Computing (SRAIC 2019)

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Random numbers play a significant role while implementing the crypto architectures on reconfigurable hardware. Chaotic attractors are reliable sources of deterministic random number generation due to their large keyspace capability. Chaos exhibits random perturbations in floating-point units which is a challenge while replicating the system of equations on hardware. The conversion of floating-point numbers to binary representation will take many quantization possibilities which certainly affect the randomness and sensitivity to initial conditions. This work aims to implement the chaotic Rössler attractor based Pseudo Random Number Generation (PRNG) on FPGA through simulation and real time experimentation. This attractor has been realized on Altera Cyclone II EP2C20F484C7 FPGA using hardware primitives. It required 201 LUTs with a power dissipation of 78.48 mW and time duration of 4 µS to generate 32,768 random bits. The randomness of this attractor was evaluated through entropy, correlation, bit distribution and NIST SP 800-22 analyses.

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Rössler-based chaotic communication system implemented on FPGA

Cited by 21 publications

References 4 publications

FPGA implementation of orthogonal hyperchaotic sequences generator based on the CNN: application in multi-user chaotic communications

FPGA implementation of orthogonal hyperchaotic sequences generator based on the CNN: application in multi-user chaotic communications

On-the-Fly Parallel Processing IP-Core for Image Blur Detection, Compression, and Chaotic Encryption Based on FPGA

Attractor Influenced Prng for Cryptographic Key Generation on FPGA

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