ROM-Based Direct Digital Synthesizer at 24 GHz Clock Frequency in InP DHBT Technology

Turner, S.E.; Chan, Richard T.; Feng, Jia-Wei

doi:10.1109/lmwc.2008.2001025

Cited by 27 publications

(12 citation statements)

References 8 publications

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“…列行 0 1 2 3 4 5 6 7 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1 2 0 0 1 1 0 0 0 1 3 0 0 1 与本文观察到现象类似 , 当同一列的数据为 "1111111011111110", 未被选中存储单元的漏电流减少位线上电流幅度 , 寄生电容的充放电时间增加 [11] . 当输出序列为一长串"0"与少数"1", 或者相反 [1] InP HBT [11] CMOS [9] GaAs HBT [8] GaAs HBT [10] GaAs HBT (本文)…”

Section: 电路设计与分析unclassified

“…只读存储器 (read-only memory) [1] 、基于算术运算 (computational mapping) [2,3] 与基于算术运算的相位幅度转换电路 [3] 相比, 采用只读存储器与算术运算相结合的方法 [7] 可获得更高的无杂散动态范围. 但只读存储器工作速度达到合成频率的 2.5 倍 [8] , 成为直接数字频率合成器的速度瓶颈.…”

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应用于直接数字频率合成器的6-GHz GaAs HBT只读存储器

陈建武¹,

王丽²,

吴旦昱³

et al. 2011

Chin. Sci. Bull.

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Section: 电路设计与分析unclassified

unclassified

应用于直接数字频率合成器的6-GHz GaAs HBT只读存储器

陈建武¹,

王丽²,

吴旦昱³

et al. 2011

Chin. Sci. Bull.

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“…This is true in some communication applications as well. One way to solve this problem is to use a high speed DDS chip [4,5,6]. Though these DDS chips have very high sampling frequency, the frequency resolution is too low or the chip is not commercial.…”

Section: Introductionmentioning

confidence: 99%

An ultra-high ramp rate arbitrary waveform generator for communication and radar applications

Zhang

Xie

Wang

et al. 2015

IEICE Electron. Express

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Currently, the frequency ramp rate of most commercial direct digital synthesizer (DDS) chips is not more than several hundred MHz. In some communication or radar applications, the frequency ramp rate must reach several GHz. In order to greatly increase the frequency ramp rate, this paper proposes a full-custom multi-core & single-channel DDS (MCSC-DDS). This MCSC-DDS consists of some DDS sub-cores which are implemented in a field programmable gate array (FPGA) and a high speed digital analog converter (DAC) whose sampling frequency achieves several GHz. In FPGA, these DDS sub-cores operate in parallel to equivalent achieve ultra-high frequency ramp rate which is equal to the sampling frequency of the DAC. As an example, a compact and portable MCSC-DDS whose frequency ramp rate achieves 2.5 GHz is presented. It is mainly made up of a Virtex-5 FPGA and an AD9739. The measured chirp waveform has a maximum 2.5 GHz frequency ramp rate which demonstrates the efficiency of the MCSC-DDS.

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“…• Frequency points : This DDS has 12-bits phase resolution which is capable of generating F P = 2 12−1 = 2048 frequency points which is largest number (jointly with [4]) in DDS beyond 15 GHz clock [59]. Other reported DDS has the maximum phase resolution of 8-bit (128 frequency points) for such high speed DDS [43].…”

Section: Technology Selection and Goalsmentioning

confidence: 96%

“…Dieses DDS hat den höchsten Takt (18,5GHz) in der SiGe-Technologie und den dritthöchsten Takt (nach [3], [4]) unter allen anderen Technologien. Einer der Hauptgründe dafür, dass [3] (32 GHz), [4] (24 GHz) wegen des schnelleren Knotens einen höheren Takt haben, nämlich f T = 350 GHz im Vergleich zu 180 GHz in diesem DDS. Dies ist das erste bisher gemeldete gemessene Phasenrauschen des Ausgangs des Hochgeschwindigkeits-DDS (>10 GHz Takt).…”

Section: Dds Ergebnisseunclassified

SiGe based ROM-less 18.5 GHz clock direct digital synthesizer design and characterization

Shrestha¹

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The requirement of the versatile signal generator has always been evident in modern RF and communication systems. The most conventional technique, voltage control oscillator (VCO), has inferior phase noise and narrow bandwidth despite its operating frequency can be up to the sub-THz regime. Its phase noise influenced by a various parameter associated with the oscillator circuit e.g. transistor size \& noise, bias current, noise leaking from the bias supply etc. The bandwidth is limited because the input voltage \& the output frequency of the VCO is not strictly linear over the tuning range. The phase noise and SFDR of the VCO output are enhanced by using the phase-lock technique. The phase-locked loop (PLL) uses the feedback system locking the reference frequency set by the VCO. However, the settling time of the PLL is higher due to a feedback control loop. The higher settling time increases the frequency switching time between PLL outputs. IG-oscillators is suitable for multi-GHz range and wide bandwidth application. Signal generation can alos be achieved by the free-electron radiation, optical lasers, Gunn diodes as well and they can operate even at the THz domain. All these signal generators suffer from slow frequency switching, lack of digital controllability, and advance modulation capability even though their frequency of operation is THz regime. Alternatively, the AWG (arbitrary wave generator) can produce a wide range of frequencies with low phase noise, including digital controllability. One of the vital components of the AWG is the direct digital synthesiser (DDS). Generally, it is composed of a phase accumulator, digital to analogue converter, sine mapping circuits and low pass filter. It needs a reference clock that acts as samples of the DDS outputs. Its output frequency can be varied by applying an appropriate digital input code. But high-speed DDS has several limitations; such as low number of output frequency points, lack of phase control unit, high power consumptions etc. This work addresses such limitations.

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ROM-Based Direct Digital Synthesizer at 24 GHz Clock Frequency in InP DHBT Technology

Cited by 27 publications

References 8 publications

应用于直接数字频率合成器的6-GHz GaAs HBT只读存储器

应用于直接数字频率合成器的6-GHz GaAs HBT只读存储器

An ultra-high ramp rate arbitrary waveform generator for communication and radar applications

SiGe based ROM-less 18.5 GHz clock direct digital synthesizer design and characterization

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