Role of Carrier Transport in Source and Drain Electrodes of High-Mobility MOSFETs

Tsuchiya, Hiroyuki; Maenaka, A.; Mori, Toshiyuki; Azuma, Yasuo

doi:10.1109/led.2010.2040024

Cited by 47 publications

(32 citation statements)

References 15 publications

(31 reference statements)

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“…The drain voltage, V ds , is 0.6 V. It is shown that the device with the InP channel exhibits the larger I ds than those with the In 0.53 Ga 0.47 As and GaAs channels, which is opposite to the prospect that the smaller m* would result in the larger I ds . The similar results have been reported by other quantum-corrected MC simulations [4].…”

Section: Simulation Methodssupporting

confidence: 91%

“…The channel length of Si MOSFETs has continued to shrink rapidly down to a sub-10-nm regime, which has opened a possibility of quasi-ballistic operation of Si MOSFETs and also has brought about an increasing focus on their fundamental performance limits [1]. Recently, III-V semiconductors as InGaAs have attracted much attention as promising n-type channel materials for the future logic device to enter the CMOS roadmap beyond Si, because of their higher carrier mobility [2][3][4]. We have showed the larger electron injection velocity originated from the smaller electron effective mass, m*, in the InGaAs channel by means of the quantum-corrected Monte Carlo (MC) simulation [5,6].…”

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confidence: 99%

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Comparative study on nano‐scale III‐V MOSFETs with various channel materials using quantum‐corrected Monte Carlo simulation

Homma

Hasegawa

Watanabe

et al. 2011

Phys. Status Solidi C

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We investigate the ability of the nano‐scale III‐V MOSFETs with InGaAs, GaAs or InP channels by using the quantum‐corrected Monte Carlo (MC) simulation. The InGaAs channel shows the largest average electron velocity at the bottleneck, vs, because of the smallest electron effective mass, m * in the Γ valley. However, it is degraded by the electron rebound from the drain through the accumulation in the L valleys, when the gate voltage, Vgs, is highly biased. The electron rebound is more pronounced in the GaAs channel, because of the narrow Γ ‐ L valley separation. Meanwhile, the InP channel shows the smallest vs because of the largest m * in the Γ valley. However, the electron rebound is less pronounced, because of the smaller accumulation in the L valleys. On the other hand, the electron density at the potential bottleneck, nb, is largest in the InP channel, because of the largest gate capacitance owing to the highest density of states, DOS. Eventually, the InP channel shows the largest drain current, Ids (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

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Section: Simulation Methodssupporting

confidence: 91%

mentioning

confidence: 99%

Comparative study on nano‐scale III‐V MOSFETs with various channel materials using quantum‐corrected Monte Carlo simulation

Homma

Hasegawa

Watanabe

et al. 2011

Phys. Status Solidi C

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“…The ITRS stated that MOSFETs will be expected to have a saturation drain current (I d ) that is as high as 2 A/mm. To satisfy this requirement using a III-V channel, the source doping concentration must be greater than ~5 × 10 19 cm í3 (7).However, this is difficult to realize using ion implantation technologies for III-V materials. A possible solution is a MOSFET with regrown source and drain(S/D) structures (8), (9) so that the transconductance (g m ) and I d are high; such MOSFETs can be used to realize high-speed and low-power-consumption devices.…”

Section: Introductionmentioning

confidence: 99%

Submicron InP/InGaAs composite channel MOSFETs with selectively regrown N<sup>+</sup>-source/drain buried in channel undercut

Kanazawa

Wakabayashi

Saito

et al. 2010

2010 22nd International Conference on Indium Phosphide and Related Materials (IPRM)

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We demonstrated a high-mobility InP 5 nm/InGaAs 12 nm composite channel MOSFET with MOVPE regrown n + -source/drain region for low series resistance and high source injection current. A gate dielectric was SiO 2 and thickness was 20 nm. A carrier density of regrown InGaAs source/drain layer was over 4 × 10 19 cm í3 . In the measurement of submicron (= 150 nm) device, the drain current was 0.93 mA/μm at V g = 3 V, V d = 1 V and the peak transconductance was 0.53 mS/ȝm at V d = 0.65 V, respectively. The channel length dependence of transconductance indicated the good relativity.

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“…For high performance III-V channel MOSFETs, the source/drain (S/D) region with a low resistance is remained as one challenge because of the limited dopant solubility and activation rate [2]. The metal Schottky S/D structure is a promising solution due to the low resistance and low temperature process.…”

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confidence: 99%

InP Schottky Barrier MOSFET with TiO2/Al2O3 as Gate Oxide

Lee

Yen

2014

2014 International Symposium on Computer, Consumer and Control

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The characteristics of Al/InP Schottky diode without and with (NH 4 ) 2 S treatment (Al/S-InP) and corresponding MOSFET with atomic layer deposited TiO 2 /Al 2 O 3 stacked gate oxides were investigated. The Schottky barrier height (I Bp ) of Al/InP with (NH 4 ) 2 S treatment is improved from the removal of native oxides. For Al/S-InP Schottky barrier MOSFET with TiO 2 /Al 2 O 3 gate oxides, good drain currentvoltage and sub-threshold characteristics were obtained. The channel mobility and transconductance can reach 202 mm 2 /Vs and 4.45 × 10 -7 S/μm at V DS = 1 V. Keywords-Schottky barrier, ALD, Al 2 O 3 , TiO 2 , InP, MOSFET I. INTRODUCTION ecently, III-V compound semiconductor MOSFETs have attracted strong attention as the scaling of Si CMOS technology beyond the 22 nm node for their higher electron mobility than Si-based counterparts [1]. For high performance III-V channel MOSFETs, the source/drain (S/D) region with a low resistance is remained as one challenge because of the limited dopant solubility and activation rate [2]. The metal Schottky S/D structure is a promising solution due to the low resistance and low temperature process.The gate dielectric with low interface state density (D it ), and good thermal stability is also essential for high performance MOSFET. Many high-k dielectrics are currently being explored on InP. TiO 2 has a relatively high dielectric constant (k value 35-100 depending on the growth method) and high transconductance MOSFET with TiO 2 gate oxide is expected. However, the high thermionic emission of low band-gap TiO 2 (3.5 eV) needs a high band-gap, for example Al 2 O 3 (9 eV) stacked on it. Films with precise thickness can be prepared by atomic layer deposition (ALD), in which selflimiting precursors are sequentially deposited [3]. ALD offers higher quality thin film on atomic scale over conventional MOCVD (metal-organic chemical vapor deposition). In addition, ALD-Al 2 O 3 on III-V compound can improve the interface quality by the self-cleaning reaction on native oxides [4], which is the main contribution to high interface state density (D it ) [5]. High D it will cause the Fermi-level pinning at the interfaces of Schottky S/D and gate oxide on III-V

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Role of Carrier Transport in Source and Drain Electrodes of High-Mobility MOSFETs

Cited by 47 publications

References 15 publications

Comparative study on nano‐scale III‐V MOSFETs with various channel materials using quantum‐corrected Monte Carlo simulation

Comparative study on nano‐scale III‐V MOSFETs with various channel materials using quantum‐corrected Monte Carlo simulation

Submicron InP/InGaAs composite channel MOSFETs with selectively regrown N<sup>+</sup>-source/drain buried in channel undercut

InP Schottky Barrier MOSFET with TiO2/Al2O3 as Gate Oxide

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Role of Carrier Transport in Source and Drain Electrodes of High-Mobility MOSFETs

Cited by 47 publications

References 15 publications

Comparative study on nano‐scale III‐V MOSFETs with various channel materials using quantum‐corrected Monte Carlo simulation

Comparative study on nano‐scale III‐V MOSFETs with various channel materials using quantum‐corrected Monte Carlo simulation

Submicron InP/InGaAs composite channel MOSFETs with selectively regrown N<sup>&#x002B;</sup>-source/drain buried in channel undercut

InP Schottky Barrier MOSFET with TiO2/Al2O3 as Gate Oxide

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Submicron InP/InGaAs composite channel MOSFETs with selectively regrown N<sup>+</sup>-source/drain buried in channel undercut