Role of 3D photo-resist simulation for advanced technology nodes

Samy, Aravind Narayana; Seltmann, Rolf; Kahlenberg, Frank; Schramm, Jessy; Küchler, Bernd; Klostermann, Ulrich

doi:10.1117/12.2011427

Cited by 8 publications

(8 citation statements)

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“…For weak-points that represent very critical design situations, the profile might be disturbed despite its correct CD. Figure 2 shows profiles printing at the same nominal CD but being critical at either bottom, top or having insufficient resist height to allow uniform etch resistivity [1]. Such defects demand a consideration of resist 3D effects both in defect recognition and in defect repair (or hotspot fix).…”

Section: Introductionmentioning

confidence: 96%

“…So this 3D aware model is used in the application to insert the defect insertion point and in the investigation of detected defects not only restricted to post litho but also in further steps by correlating 3D profile information with the post etch/CMP defects. This further enhances its application as virtual process development tool, best focus tuning, and investigation of detected defects and also in ORC hotspot verifications[1]. It's also clear fromfigure 6, the strong profile -F defocus -40.…”

mentioning

confidence: 92%

“…Figure 3 shows the dataflow for resist model and its calibration. We can see that the lithographic simulation is an optical simulation from mask to image and a resist simulation from image to developed resist profile [1]. Figure 3.…”

Section: Introductionmentioning

confidence: 99%

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Challenges in process marginality for advanced technology nodes and tackling its contributors

et al. 2013

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Process margin is getting critical in the present node shrinkage scenario due to the physical limits reached (Rayleigh's criterion) using ArF lithography tools. K1 is used to its best for better resolution and to enhance the process margin (28nm metal patterning k1=0.31). In this paper, we would like to give an overview of various contributors in the advanced technology nodes which limit the process margins and how the challenges have been tackled in a modern foundry model.Advanced OPC algorithms are used to make the design content at the mask optimum for patterning. However, as we work at the physical limit, critical features (Hot-spots) are very susceptible to litho process variations. Furthermore, etch can have a significant impact as well. Pattern that still looks healthy at litho can fail due to etch interactions. This makes the traditional 2D contour output from ORC tools not able to predict accurately all defects and hence not able to fully correct it in the early mask tapeout phase. The above makes a huge difference in the fast ramp-up & high yield in a competitive foundry market. We will explain in this paper how the early introduction of 3D resist model based simulation of resist profiles (resist top-loss, bottom bridging, top-rounding, etc.,) helped in our prediction and correction of hot-spots in the early 28nm process development phase. The paper also discusses about the other overall process window reduction contributors due to mask 3D effects, wafer topography (focus shifts/variations) and how this has been addressed with different simulation efforts in a fast and timely manner.

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Section: Introductionmentioning

confidence: 96%

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confidence: 92%

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Challenges in process marginality for advanced technology nodes and tackling its contributors

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“…The authors adopted the quasi-3D resist model approach to obtain the resist sidewall angle and to mitigate the wafer-to-model errors [1]. Samy et al demonstrated a rigorous resist model calibration and the verification with top-down CD SEM, AFM and cross-section SEM [7]. In response to Samy's work, Fan et al further extended the application to full-chip simulation by matching the 2D compact model in 2 different imaging planes to the rigorous resist model [8].…”

Section: Introductionmentioning

confidence: 99%

Resist profile simulation with fast lithography model

Chou

Tang

et al. 2014

SPIE Proceedings

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A traditional approach to construct a fast lithographic model is to match wafer top-down SEM images, contours and/or gauge CDs with a TCC model plus some simple resist representation. This modeling method has been proven and is extensively used for OPC modeling. As the technology moves forward, this traditional approach has become insufficient in regard to lithography weak point detection, etching bias prediction, etc. The drawback of this approach is from metrology and simulation. First, top-down SEM is only good for acquiring planar CD information. Some 3D metrology such as cross-section SEM or AFM is necessary to obtain the true resist profile. Second, the TCC modeling approach is only suitable for planar image simulation. In order to model the resist profile, full 3D image simulation is needed. Even though there are many rigorous simulators capable of catching the resist profile very well, none of them is feasible for full-chip application due to the tremendous consumption of computational resource. The authors have proposed a quasi-3D image simulation method in the previous study [1], which is suitable for full-chip simulation with the consideration of sidewall angles, to improve the model accuracy of planar models.In this paper, the quasi-3D image simulation is extended to directly model the resist profile with AFM and/or cross-section SEM data. Resist weak points detected by the model generated with this 3D approach are verified on the wafer.

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“…On the one hand, the advanced process development requires detailed R3D information in order to investigate the limitations and optimize the process. On the other hand, it has become necessary to build the resist profile information into the so-called R3D optical proximity correction (OPC) compact model [7][8][9][10][11][12] which traditionally only contains 2D information in the x-y plane. Therefore a reliable model with capability of correct prediction of R3D is acquiring higher importance.…”

Section: Introductionmentioning

confidence: 99%

Experimental validation of rigorous, 3D profile models for negative-tone develop resists

et al. 2014

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The extension of 193nm immersion lithography to the 14nm node and beyond directly encounters a significant reduction in image quality. One of the consequences is that the resist profile varies noticeably, impacting the already limited process window. Resist top-loss, top-rounding, T-top and footing all play significant roles in the subsequent etch process. Therefore, a reliable rigorous model with the capability to correctly predict resist 3D (R3D) profiles is acquiring higher importance. In this paper, we will present a calibrated rigorous model of a negative-tone develop resist. Resist profiles can be well simulated through focus and dose, and cases that match well to the experimental wafer data are validated. Such a model can not only provide early investigation of insights into process limitation and optimization, but can also complement existing OPC models to become R3D-aware in process development.

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Role of 3D photo-resist simulation for advanced technology nodes

Cited by 8 publications

References 0 publications

Challenges in process marginality for advanced technology nodes and tackling its contributors

Challenges in process marginality for advanced technology nodes and tackling its contributors

Resist profile simulation with fast lithography model

Experimental validation of rigorous, 3D profile models for negative-tone develop resists

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