Robustness of CNT Via Interconnect Fabricated by Low Temperature Process over a High-Density Current

Kawabata, Akio; Sato, Shintaro; Nozue, Tatsuhiro; Hyakushima, Takashi; Norimatsu, M.; Mishima, Miho; Murakami, T.; Kondo, Daiyu; Asano, Koji; Ohfuti, Mari; Kawarada, Hiroshi; Sakai, Tadashi; Nihei, Misato; Awano, Yuji

doi:10.1109/iitc.2008.4546977

Cited by 37 publications

(22 citation statements)

References 3 publications

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“…• C, and with this low temperature growth, the integration of CNT via structure in ultralow k dielectric (k = 2.6) with good reliability performance has also been demonstrated [31]. All of these progresses indicate the technological feasibility of CNT interconnects.…”

Section: Cnt-based On-chip Inductormentioning

confidence: 82%

High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design

Lei

Banerjee

2009

IEEE Trans. Electron Devices

148

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Abstract-This paper presents a rigorous investigation of highfrequency effects in carbon nanotube (CNT) interconnects and their implications for the design and performance analysis of highquality on-chip inductors. A frequency-dependent impedance extraction method is developed for both single-walled CNT (SWCNT) and multiwalled CNT (MWCNT) bundle interconnects. The method is subsequently verified by comparing the results with those derived directly from the Maxwell's equations. Our analysis reveals for the first time that skin effect in CNT (particularly MWCNT) bundles is significantly reduced compared to that in conventional metal conductors, which makes them very attractive and promising material for high-frequency applications, including high-quality (Q) factor on-chip inductor design in highperformance RF/mixed-signal circuits. It is shown that such unique high-frequency properties of CNTs essentially arise due to their large momentum relaxation time (leading to their large kinetic inductance), which causes the skin depths to saturate with frequency and thereby limits resistance increase at high frequencies in a bundle structure. It is subsequently shown that CNTbased planar spiral inductors can achieve more than three times higher Q factor than their Cu-based counterparts without using any magnetic materials or Q factor enhancement techniques.Index Terms-AC conductivity, carbon nanotube (CNT), energy storage, high-frequency, interconnect, momentum relaxation time, on-chip inductor, Q factor, skin depth, skin effect.

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Section: Cnt-based On-chip Inductormentioning

confidence: 82%

High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design

Lei

Banerjee

2009

IEEE Trans. Electron Devices

148

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“…Low temperature growth in via holes has been reported by use of a "remote" plasma CVD method [24] and cobalt clusters as catalyst. The plasma energy promotes the gas cracking and help in lowering the temperature growth.…”

Section: Device Fabricationmentioning

confidence: 99%

“…At low voltages below 1V, the resistivity increases dramatically up to 3.10 -2 Ω.cm. In the literature, 4.8*10 -4 Ω.cm resistivity values are reported by Awano et al by using nanotubes at low voltages [24] whereas 5*10 -5 Ω.cm is the best resistivity measured by Ngo et al using nanofibres at low voltages [28]. The resistance per nanotube is found to be 20 kΩ at low voltage [39].…”

Section: Room Temperature Measurements On Multiwall Carbon Nanotube Bmentioning

confidence: 99%

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An application of carbon nanotubes for integrated circuit interconnects

Coiffic¹,

Torres²,

Poche

et al. 2008

Carbon Nanotubes and Associated Devices

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Integrated circuits fabrication is soon reaching strong limitations. Help could come from using carbon nanotubes as conducting wires for interconnects. Although this solution was proposed six years ago, researchers still come up with many obstacles such as localization, low temperature growth on copper, contacting and reproducibility. The integration processes exposed here intend to meet the industrial requirements. Two approaches are then possibly followed. Either using densely packed single wall (SWCNT) (or very tiny multiwall) nanotubes, or filling up the whole interconnect diameter with a single large multiwall (MWCNT) nanotube. In this work, we focus on the integration of multiwall vertical interconnects. Densely packed MWCNTs are grown in via holes by CVD. Alternatively, we have developed a method to obtain a single large nanofibre grown by PECVD (MWCNF) in each via hole. Electrical measurements are performed on CVD and PECVD grown carbon nanotubes. The role of electron-phonon interaction in these devices is also briefly discussed.

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“…al. have shown [6,7] that the CNT bundle could grow on top of metal line through SiO 2 vias (BEOL) of diameter as low as 2 m with CNT density of 1.6×10 11 cm -2 at 390 o C. They demonstrate that after chemical mechanical polishing (CMP) the resistance of CNT bundle falls from 32 to 0.9 , possibly due to involvement of all interior walls of a MWCNT into good electrical contact. It has also been demonstrated that the density of the CNT bundle could possibly be enhanced [8] via wet chemical densification process to 2.5×10 12 cm -2 .…”

Section: Introductionmentioning

confidence: 99%

Integration of CNT in TSV (≤5 μm) for 3D IC application and its process challenges

Ghosh

Yap

Tay

et al. 2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

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The availability of high density TSVs depends on how smart we miniaturize the interconnect dimension in 3D IC package. A number of considerations include controllable TSV aspect ratio, pitch, and material selection. The International Technology Roadmap for Semiconductors (ITRS) has proposed scaling of TSV diameter down to as low as 2 m in the future. However, with TSV scaling, the resistance of the TSV increases significantly. Carbon nanotubes (CNTs) could be a potential alternative material to Cu for VLSI interconnects applications, including TSV, due to their outstanding electrical, mechanical, and thermal properties. Here, we demonstrate a method to integrate carbon nanotubes (CNTs)-filled TSV under 5 μm diameter that are connected by metal-lines at the bottom and show the facile route of fabrication at low temperature regime. The process challenges are highlighted. Keywords-Carbon nanotube, Through-silicon via, 3D-IC, Wafer bondingI.

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Robustness of CNT Via Interconnect Fabricated by Low Temperature Process over a High-Density Current

Cited by 37 publications

References 3 publications

High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design

High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design

An application of carbon nanotubes for integrated circuit interconnects

Integration of CNT in TSV (≤5 μm) for 3D IC application and its process challenges

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Robustness of CNT Via Interconnect Fabricated by Low Temperature Process over a High-Density Current

Cited by 37 publications

References 3 publications

High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design

High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design

An application of carbon nanotubes for integrated circuit interconnects

Integration of CNT in TSV (&#x2264;5 &#x03BC;m) for 3D IC application and its process challenges

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Product

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Integration of CNT in TSV (≤5 μm) for 3D IC application and its process challenges