“…This provides an execution model of the crosslayer RaS procedures which is enabled by the use of IJTAG networks for sensor/actuator access and control since physical Paper ITC-Asia. 3 INTERNATIONAL TEST CONFERENCE…”
Section: Using Ijtag Network For a Hierarchical And Cross-layer Execu...mentioning
confidence: 99%
“…A System-DM (SDM) is shown to be incorporated at the top level of the network, and hence, can access and control all the EIs on Paper ITC-Asia. 3 INTERNATIONAL TEST CONFERENCE A DM is considered as an instrument itself. The System-DM and the Cluster-DMs incorporate a set of Test Data Registers (TDRs) in order to be able to communicate with the higherlevel controller.…”
Section: A the Ras Design Layermentioning
confidence: 99%
“…For example, in [45] a methodology was presented for optimally organizing the SIB hierarchy according to the access schedules of instruments, where instruments with Paper ITC-Asia. 3 INTERNATIONAL TEST CONFERENCE a stricter latency requirement are placed higher in the hierarchy to reduce their access time.…”
Section: Network Generationmentioning
confidence: 99%
“…SoCs are being increasingly used in safety-and missioncritical domains such as automotive, medical and space. Such applications require a dependable operation along with a prolonged lifetime, as in the case of Advanced Driving Assistance Systems (ADAS) [3]. Consequently, several dedicated software solutions have been previously proposed for maintaining the Reliability and functional Safety of SoCs using Embedded Instruments (EIs).…”
Electronic design automation tools used for Design-For-Test infrastructure insertion have often relied on test standards (e.g. IEEE 1149.1, 1500 and 1687) as a structured methodology for IC test access, which consequently reduce the design cost for DFT. The IEEE 1687 standard introduces an efficient methodology for the off-chip access of the increasing number of embedded instruments that are used for test, debug and other purposes. A subset of these instruments is also used for Reliability and functional Safety (RaS) management, while accessing them via an on-chip manager. In this paper, we present a design automation framework for the RaS management of System-on-Chips using embedded instruments, by utilizing the IEEE 1687 standard as the key enabler of this automation. The framework enables the on-chip execution of cross-layer RaS procedures by the automatic generation of a dedicated design layer for the procedures execution. The framework utilizes the IEEE 1687-defined PDL language and the pattern retargeting process for enabling a programming model for developing the RaS procedures with no regard to the instruments access procedures and their physical locations, which consequently reduce the development time of RaS procedures and enable their scalability and reusability, and hence their automation.
“…This provides an execution model of the crosslayer RaS procedures which is enabled by the use of IJTAG networks for sensor/actuator access and control since physical Paper ITC-Asia. 3 INTERNATIONAL TEST CONFERENCE…”
Section: Using Ijtag Network For a Hierarchical And Cross-layer Execu...mentioning
confidence: 99%
“…A System-DM (SDM) is shown to be incorporated at the top level of the network, and hence, can access and control all the EIs on Paper ITC-Asia. 3 INTERNATIONAL TEST CONFERENCE A DM is considered as an instrument itself. The System-DM and the Cluster-DMs incorporate a set of Test Data Registers (TDRs) in order to be able to communicate with the higherlevel controller.…”
Section: A the Ras Design Layermentioning
confidence: 99%
“…For example, in [45] a methodology was presented for optimally organizing the SIB hierarchy according to the access schedules of instruments, where instruments with Paper ITC-Asia. 3 INTERNATIONAL TEST CONFERENCE a stricter latency requirement are placed higher in the hierarchy to reduce their access time.…”
Section: Network Generationmentioning
confidence: 99%
“…SoCs are being increasingly used in safety-and missioncritical domains such as automotive, medical and space. Such applications require a dependable operation along with a prolonged lifetime, as in the case of Advanced Driving Assistance Systems (ADAS) [3]. Consequently, several dedicated software solutions have been previously proposed for maintaining the Reliability and functional Safety of SoCs using Embedded Instruments (EIs).…”
Electronic design automation tools used for Design-For-Test infrastructure insertion have often relied on test standards (e.g. IEEE 1149.1, 1500 and 1687) as a structured methodology for IC test access, which consequently reduce the design cost for DFT. The IEEE 1687 standard introduces an efficient methodology for the off-chip access of the increasing number of embedded instruments that are used for test, debug and other purposes. A subset of these instruments is also used for Reliability and functional Safety (RaS) management, while accessing them via an on-chip manager. In this paper, we present a design automation framework for the RaS management of System-on-Chips using embedded instruments, by utilizing the IEEE 1687 standard as the key enabler of this automation. The framework enables the on-chip execution of cross-layer RaS procedures by the automatic generation of a dedicated design layer for the procedures execution. The framework utilizes the IEEE 1687-defined PDL language and the pattern retargeting process for enabling a programming model for developing the RaS procedures with no regard to the instruments access procedures and their physical locations, which consequently reduce the development time of RaS procedures and enable their scalability and reusability, and hence their automation.
“…SoCs are being increasingly used in safety-and missioncritical domains such as automotive, medical and space. Such applications require a dependable operation along with a prolonged lifetime, as in the case of Advanced Driving Assistance Systems (ADAS) [1]. Consequently, several dedicated software solutions have been previously proposed for maintaining the Reliability and functional Safety (RaS) of SoCs using EIs.…”
The IEEE 1687 standard defines a standardized mechanism for the off-chip access of embedded instruments. A subset of these instruments are also used for maintaining the reliability and functional safety of the chip during its lifetime. For example, temperature sensors, voltage monitors and Built-In-Self-Test engines. In this paper, we present a novel on-chip controller for IEEE 1687 networks which can execute instrument procedures documented in the IEEE 1687 PDL language. These procedures are incorporated within the reliability and functional safety embedded software that uses the measurements data of the instruments. The controller includes an efficient structural model of the IEEE 1687 network and can perform on-chip pattern retargeting on arbitrary networks. In addition, it can perform localization of instrument interrupts that are propagated via multi-mode IEEE 1687 networks.
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