Robust high speed ASIC design of a vedic square calculator using ancient Vedic mathematics

Khan, Angshuman; Sur, Surajit; Gupta, Chitra; Bandyopadhyay, Moulina; Pramanik, Sayak; Saha, Souvik; Verma, Ankit; Samanta, Asmita; Singha, Sudip Kumar

doi:10.1109/iemcon.2017.8117240

Cited by 3 publications

(6 citation statements)

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“…The output P= P0P1P2P3 is four bits where carry C1 is coming from second step and carry (C2) in last step is the MSB of sum (P3). The plan of Vedic calculator using the above described technique is proposed recently [17] and the architecture is shown in Fig. 2.…”

Section: Proposed Designmentioning

confidence: 99%

“…The projected design (as shown in Fig. 3) contains of only two XOR gates and one AND gate unlike the recently proposed [17] squarer where two AND gates and two Half adders are used. Here the input is X= X0X1 (two bits) and the result is P= P0P1P2P3 (four bits).…”

Section: Proposed Designmentioning

confidence: 99%

“…The projected Vedic square calculator has been designed here and it has been simulated successfully. With analysing the simulation report and device utilization summary of the proposed squarer, it has been compared to the popular already proposed [17] architecture as shown in TABLE I. The performance of the projected improved design exactly same as its main architecture [17], but advantage is that the area usage is very lesser as only 3 digital gates are sufficient to complete the design instead of 6 gates.…”

Section: Comparisonsmentioning

confidence: 99%

“…The multiplier model to multiply special numbers is also noteworthy here [15][16]. But among all discussed multipliers, the recent ASIC square calculator is well accepted [17].…”

Section: Introductionmentioning

confidence: 99%

“…A new modified architecture of recently proposed multiplier [17], which is the simplest and minimized one for square calculation, is designed here for Application Specific Integrated Circuit (ASIC). But the design proposed here includes only a few number of fun-damental digital logic gates by successfully applying the concept of Vedic formula.…”

Section: Introductionmentioning

confidence: 99%

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Design of ASIC Square Calculator Using AncientVedic Mathematics

Khan¹,

Halder²,

Pal³

2018

IJET

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This article includes a simple design of Vedic square calculator for Application Specific Integrated Circuit (ASIC). This is a straightforward and innovative design of Vedic calculator using only few basic digital logic gates. Among the all sutras and sub sutras of ancient Vedic mathematics, the sutra ‘Urdhva Tiryagbyham’ is used here for square calculation of two bits numbers which results in an effortless and faster method of square calculation than all the existing methods. The design and minimization of the circuit has been carried out to achieve a standard architecture that is the simplest too. Here Xilinx ISE software tool is used rigorously to simulate the architecture.

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Section: Proposed Designmentioning

confidence: 99%

Section: Proposed Designmentioning

confidence: 99%

Section: Comparisonsmentioning

confidence: 99%

“…The multiplier model to multiply special numbers is also noteworthy here [15][16]. But among all discussed multipliers, the recent ASIC square calculator is well accepted [17].…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations