Robust gate sizing via mean excess delay minimization

Cong, Jason; Lee, John; Vandenberghe, Lieven

doi:10.1145/1353629.1353634

Cited by 7 publications

(3 citation statements)

References 26 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The modeling of the gate sizing problem using the interconnect delay model can address the impact of process variations due to interconnects, but it may not accurately handle the variations in gate geometries. The delay models based upon the gate geometries such as the ones presented in Mahalingam et al [2008], Mani and Orshansky [2004], Bhardwaj and Vrudhula [2008], and [Cong et al 2008] tune the transistor parameters, and thus more closely model the variations in gate sizes. In Bhardwaj and Vrudhula [2008] the authors identify each variation component (L eff , W , V th , T ox ) as a Gaussian, and identify the mean and the variance values for each component.…”

Section: Mathematical Programming Methodsmentioning

confidence: 99%

Variation-aware multimetric optimization during gate sizing

Ranganathan

Gupta

Mahalingam

2009

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

The aggressive scaling of technology has not only accentuated the effects of intradie parametric variations in devices, but it has also impacted the effects of optimizing a certain performance metric on the optimality of other metrics. Thus, there is a need for optimization methods that can perform the simultaneous optimization of multiple metrics considering the effects of process variations. In this article, a novel variation-aware gate sizing framework has been developed that can perform simultaneous optimization of multiple performance metrics. In this framework, the relationships between the optimization metrics (like dynamic power, leakage power, and crosstalk noise) are modeled as a function of the gate sizes in the objective function. The delay values obtained from unconstrained delay optimization and the noise margins derived from coupling capacitance information form the constraints for the multimetric optimization problem. As an abstract framework, it is independent of the type of mathematical programming approach as well as the metrics chosen to be optimized. The framework has been implemented using a mathematical programming approach and has been tested on ITC'99 benchmarks for different combinations of multimetric and single-metric optimizations of delay, dynamic power, leakage power, and crosstalk noise. The results indicate that the framework identifies good solution points, and is efficient for postlayout optimization via gate sizing.

show abstract

Section: Mathematical Programming Methodsmentioning

confidence: 99%

Variation-aware multimetric optimization during gate sizing

Ranganathan

Gupta

Mahalingam

2009

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

show abstract

“…Other works use statistics-based approaches to capture the uncertainty stemming from PV [16][17] [18]. The spatial correlations in L ef f inherent in the PV model, however, are too complex to be captured by simple statistical models.…”

Section: Gate Sizingmentioning

confidence: 99%

Maximizing yield in Near-Threshold Computing under the presence of process variation

Conos

Meguerdichian

Wei

et al. 2013

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

View full text Add to dashboard Cite

Abstract-Near-Threshold Computing (NTC) shows potential to provide significant energy efficiency improvements as it alleviates the impact of leakage in modern deep sub-micron CMOS technology. As the gap between supply and threshold voltage shrink, however, the energy efficiency gains come at the cost of device performance variability. Thus, adopting nearthreshold in modern CAD flows requires careful consideration when addressing commonly targeted objectives. We propose a process variation-aware near-threshold voltage (P V -Nvt) gate sizing framework for minimizing power subject to performance yield constraints. We evaluate our approach using an industrialflow on a set of modern benchmarks. Our results show our method achieves significant improvement in leakage power, while meeting performance yield targets, over a state-of-the-art method that does not consider near-threshold computing.

show abstract

“…There are many papers that explore the benefits of adding statistical delay data into the optimization process [4], [5]- [10], and there are also a number of papers that use a statistical power measure [7], [11]- [15]. However, to the best of our knowledge, there is no publication that shows the benefits of using the statistical power measure alone.…”

mentioning

confidence: 99%

Evaluating Statistical Power Optimization

Cong

Gupta

Lee

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

Abstract-In response to the increasing variations in integrated-circuit manufacturing, the current trend is to create designs that take these variations into account statistically. In this paper, we quantify the difference between the statistical and deterministic optima of leakage power while making no assumptions about the delay model. We develop a framework for deriving a theoretical upper bound on the suboptimality that is incurred by using the deterministic optimum as an approximation for the statistical optimum. We show that for the mean power measure, the deterministic optima is an excellent approximation, and for the mean plus standard deviation measures, the optimality gap increases as the amount of inter-die variation grows, for a suite of benchmark circuits in a 45 nm technology. For large variations, we show that there are excellent linear approximations that can be used to approximate the effects of variation. Therefore, the need to develop special statistical power optimization algorithms is questionable.

show abstract

Robust gate sizing via mean excess delay minimization

Cited by 7 publications

References 26 publications

Variation-aware multimetric optimization during gate sizing

Variation-aware multimetric optimization during gate sizing

Maximizing yield in Near-Threshold Computing under the presence of process variation

Evaluating Statistical Power Optimization

Contact Info

Product

Resources

About