Robust and Low-Power Digitally Programmable Delay Element Designs Employing Neuron-MOS Mechanism

Abstract

The feasibility of designing digitally programmable delay elements (PDEs) employing neuron-MOS mechanism is investigated in this work. By coupling the capacitors on the gate of the MOS transistor, the current flowing through the transistor can be digitally tuned without additional static power consumption. Various switching delays are generated by a clock buffer stage in this manner. Two types of neuron-MOS-based PDEs are suggested in this article. One of them is realized by directly applying capacitor-coupling technology on the transistors of an inverter as a clock buffer. The delay programmability is realized by tuning the charging/discharging current through the neuron-MOS inverter digitally. Since no additional transistor is introduced into the charging/discharging path, the performance fluctuation due to process variations on MOS transistors is reduced. The temperature effect is also partially compensated by the proposed neuron-MOS implementation. Another type of PDE circuit is proposed by employing a reliable reference-current-generator, where the neuron-MOS transistor acts as a linearly tunable resistance. A stable reference current is generated and used for charging/discharging the inverter as a clock buffer. As a result, the switching delay of the inverter is linearly programmed by digital input patterns. In general, both types of suggested PDE circuits achieve improved or fair performances over the robustness, power consumption, and linearity.

Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications

“…This is because there is a trade-off relation between delay range and the jitter performance [4]. In addition, the total delay fluctuations including jitter should be less than the delay resolution for optimum operation [5]. …”

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance

“…This is strongly correlated to the propagation delay of logic gates in any given CMOS process. Although choosing smaller feature-size transistors in DSM or UDSM technology for a high-resolution TDL design seems attractive (Zhang and Kaneko 2015 ), one must not forget the effects of interconnect resistance, negative bias temperature instability (NBTI), random doping fluctuations, gate-oxide tunneling, PVT variations and short channel effect which become more and more significant (Jiang 2011 ; Segura et al 2006 ; Ghahroodi 2014 ). These effects ultimately contribute to excessive timing jitter which should be minimized.…”

“…These effects ultimately contribute to excessive timing jitter which should be minimized. Besides that, utilizing wider transistors is not useful in enhancing the delay resolution as the gate capacitance of logic gates is increased simultaneously (Zhang and Kaneko 2015 ; Nuyts et al 2014 ). Single-output delay line architecture: …”

“…The drive strength can be changed through two main methods which are changing the power supply voltage, also called supply modulation (Nuyts et al 2014 ; Klepacki et al 2014 ; Yang 2003 ), and current-starving (Schidl et al 2012 ; Nuyts et al 2014 ; Klepacki et al 2014 ). The current-starving method can be implemented using many techniques, but the main are: adding delay-controlling MOS transistors of controlled aspect ratio which act as adjustable current sources at the pull down and/or pull up networks (Maymandi-Nejad and Sachdev 2005 ; Klepacki et al 2014 ; Henzler 2010b ; Rahkonen and Kostamovaara 1993 ), connecting additional delay-controlling MOS transistors at the output of logic gates as in the case of a transmission gate placed at the output of a logic gate (Nuyts et al 2014 ; Mahapatra et al 2002 ), employing a neuron-MOS mechanism which is based on an nMOS transistor with a gate electrode electrically floating (Zhang and Kaneko 2015 ; Shibata and Ohmi 1992 ), and employing an RC-based differentiator to drive the pMOS transistor of a CMOS inverter (El Mourabit et al 2012 ).…”

“…These delay-controlling/tuning techniques change the rate at which the output effective capacitance is charged/discharged. On the other hand, adding a variable load or sometimes referred to as load-increasing strategy (Zhang and Kaneko 2015 ) is implemented either by adding explicit tunable output capacitance(s) (Andreani et al 1999 ; Yang 2003 ; Schidl et al 2012 ) or by controlling the charging/discharging current of the node of MOS-diode at the internal node of a logic-gates-based buffer (Markovic et al 2013 ; Klepacki et al 2014 ). For analog delay elements, such as the one illustrated in Fig.…”