Robust and High-Performance 12-T Interlocked SRAM for In-Memory Computing

Surana, Neelam; Lavania, Mili; Barma, Abhishek; Mekie, Joycee

doi:10.23919/date48585.2020.9116361

Cited by 15 publications

(16 citation statements)

References 8 publications

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“…GL GR 4) Half-select issue: The half-select issue is defined as the flip of the stored value at half selected cell(row, column) during the write-back operation of IMC [12]. The C6T SRAM suffers from bit line disturbance in the row-half-selected bit cells [18].…”

Section: Rwl[2]mentioning

confidence: 99%

“…The proposed SDP8T SRAM based IMC architecture has low bit line swing and decouple read path which eliminate sneak path current and virtual ground condition lead to significantly reduction in energy consumption. When the work in C6T [6], 6TCSRAM [28] 8+T [11], 8T [14] and 10T [20], 12T [12], and 4+2T [9] are imported to 65nm, they will consume 16.29fJ/bit, 15.13fJ/bit, 27.67fJ/bit, 22.5fJ/bit, 27.94fJ/bit, 17fJ/bit and 31.8 fJ/bit (Energy ∝ T echnology 2 [20]) energy, respectively, which is 32.22%, 27.03%, 60.10%, 50.93%, 60.48%, 35.05% and 65.28% higher as compared to proposed work as observed from Table II. The proposed SDP8T-IMC architecture performs reliable IMBC operation without any disturbance and half select issue from 1 V to below 0.4 V. Therefore, the energy-efficiency of proposed IMC architecture can be futhure improved by scaling the supply voltage to subthershold regions.…”

Section: B Energy Benefitsmentioning

confidence: 99%

“…The above performance parameters have a tradeoff between them. Therefore, Figure of Merit (FOM) [12] is described in equation 2 to compare IMC architecture.…”

Section: Figure Of Meritsmentioning

confidence: 99%

“…A read computation scheme [11] has been proposed to improve the latency during IMC operation by using the 8T SRAM with a skew inverter as a sense amplifier. However, the proposed scheme suffered from compute-failure(provides false computing results) due to process variations [12]. The author in [13] has presented the sensing scheme to overcome the compute-failure in 8T SRAM for IMC operation.…”

mentioning

confidence: 99%

“…The dual-port 8T SRAM has been proposed for current-based compute-in-memory dot product operations [16]. However, the 8T SRAM [11], [13], [15], [16] still suffers from low array efficiency and halfselect issue [12] due to 6T-like write operations [17], [18]. The 10T SRAM reported in [19], [20] are free from computefailure and compute-disturb and compute all logic operations in a single cycle.…”

mentioning

confidence: 99%

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Local Bit-Line Sharing Robust Dual-Port 8T SRAM With Virtual VSS for Energy-Efficient In-Memory Computing Architecture

Rajput¹,

Pattanaik²,

Kaushal³

2021

Preprint

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The In-Memory Computing (IMC) architecture based on 6T, 8T, 10T SRAM fails under process-variation and suffers from compute-disturb, compute-failure, half-select issue, respectively, which affect the reliability of IMC operation. To overcome these problems, local bit-line sharing Dual-Port 8T (SDP8T) SRAM with Virtual VSS is proposed to improve the stability and energy efficiency of IMC architecture. The decouple read-write path with high-Vth transistor is used to improve the read-margin by 2.11× and reduce the read-energy by 36.35% as compared to Transpose-8T SRAM. The virtual VSS write assist is used in SDP8T SRAM to improve the write-margin by 26.49%, and lower the leakage power by 47.95% as compared to Transpose-8T SRAM. Furthermore, IMC architecture is proposed using SDP8T SRAM. In addition to the SRAM function, SDP8T-IMC architecture performs In-memory Boolean computation(IMBC) operations without compute-disturbance and compute-failure. The remarkable feature of SDP8T-IMC architecture is that it performs IMBC operation on four operands simultaneously using all four bit-line ports in a single cycle, thus doubling the throughput and obtain 11.04 fJ/bit average energy consumption at 1 V supply. The maximum operating frequency of the proposed IMC architecture is 1050 MHz at 1 V. Cumulatively, the proposed SDP8T-IMC architecture has 32.22%, 27.03%, 60.10%, 50.93%, 60.48%, 35.05%, and 65.28% reduction in energy consumption as compared to C6T, 6TCSRAM, 8+T, 8T, 10T, 12T, and 4+2T SRAM based IMC architectures, respectively. Moreover, the proposed IMC architecture is configured as Binary Content Addressable Memory (BCAM) for searching applications which achieves 0.60fJ energy consumption per search/bit at 1 V.

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Section: Rwl[2]mentioning

confidence: 99%

Section: B Energy Benefitsmentioning

confidence: 99%

“…The above performance parameters have a tradeoff between them. Therefore, Figure of Merit (FOM) [12] is described in equation 2 to compare IMC architecture.…”

Section: Figure Of Meritsmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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Local Bit-Line Sharing Robust Dual-Port 8T SRAM With Virtual VSS for Energy-Efficient In-Memory Computing Architecture

Rajput¹,

Pattanaik²,

Kaushal³

2021

Preprint

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Improved Arithmetic Performance by Combining Stateful and Non‐Stateful Logic in Resistive Random Access Memory 1T–1R Crossbars

Brackmann,

Ziegler,

Jafari

et al. 2023

Advanced Intelligent Systems

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Computing‐in‐memory (CIM) is a promising approach for overcoming the memory‐wall problem in conventional von‐Neumann architectures. This is done by performing certain computation tasks directly in the storage subsystem without transferring data between storage and processing units. Stateful and non‐stateful CIM concepts are recently attracting lots of interest, which are demonstrated as logical complete, energy efficient, and compatible with dense crossbar structures. However, sneak‐path currents in passive resistive random access memory (RRAM) crossbars degrade the operation reliability and require the usage of active 1 Transistor–1 Resistance (1T‐1R) bitcell designs. In this article, the arithmetic performance and reliability are investigated based on experimental measurements and variability‐aware circuit simulations. Herein, it is aimed for the evaluation of logic operations specifically with fully integrated 1T–1R crossbar devices. Based on these operations, an N‐bit full adder with optimized energy consumption and latency is demonstrated by combining stateful and non‐stateful CIM logic styles with regard to the specific conditions in active 1T–1R RRAM crossbars.

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