Robot guiding with obstacle avoidance algorithm for uncertain enviroments based on DTCNN

Albó-Canals, Jordi; Villasante-Bembibre, Jose A.; Consul-Pacareu, Sergi; Riera-Babures, J.; Vilasís-Cardona, X.

doi:10.1109/ijcnn.2010.5596709

Cited by 2 publications

(3 citation statements)

References 8 publications

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“…It is also interesting to note that the extra hardware required to implement the S&S techniques, an accumulator, would provide the reduced area option with the capacity of applying two‐template operations or LN kernels, which is not possible in the nine CC implementation. These results were successfully applied in B/W and G/S implementations and their functionality was proved in .…”

Section: Validationmentioning

confidence: 86%

Split and shift methodology on cellular processor arrays: area saving versus time penalty

Fernandez

Brea

Cabello

2012

Circuit Theory & Apps

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This paper addresses the so-called split and shift methodology. This methodology deals with the implementation of kernels of sizes that go above the physically implemented resources (local connections and weighting circuits) on synchronous cellular processor arrays (CPA), including the realization of large neighborhood operations and/or the reduction of the available hardware in order to drop the area consumption. Two main goals are pursued in the development of the methodology, namely: (1) minimum penalty at processing time and (2) absolutely no penalty at functional level. The paper presents different techniques and guidelines for the methodology application and introduces a Figure of Merit to evaluate them by relating area gains with time penalty. This, along with a kernel shape analysis, led us to propose more adequate configurations of weighting circuits and to justify the classical choice of North-East-West-South connectivity. To validate the methodology, we realize several estimates over actual physical implementations, and we propose the realization over CPAs of the spin filters, scale invariant feature transform and speeded-up robust features algorithms. A more in-depth trade-off analysis is realized over the implementation of the pixel level snakes algorithm.but it can interact with separated PEs, thanks to the propagative effects of the array dynamics of kernel application. The basic characteristic of local connectivity and its simple SIMD control makes this kind of systems very suitable for hardware implementation. However, as a consequence, the natural size of the kernels to be applied is limited to the smallest one (3 Â 3). This is, on the other hand, an important limitation in the functionality of a CPA as larger neighborhoods are needed in several image processing primitives as diffusion or low-pass filtering operations [1], halftoning [2], texture analysis [3] or matching and hit&miss operations [4], some of them used in algorithms like modern scale-and rotation-invariant feature extractors like scale invariant feature transform (SIFT) and speeded-up robust features (SURF) [5,6].As indicated, a CPA can realize global processing taking into account the whole image information thanks to the propagative effects of the architecture. According to this we can think in solving the remote neighbors interaction through the recursive application of templates. In fact, a recursive process can be summarized in the application of a large neighborhood (LN) template. Nevertheless, the inverse process, the decomposition of a LN template into minimum-sized templates is not trivial, and different approaches have been developed to deal with this issue.The challenge is then to implement any kind of LN operations while keeping the local connectivity and with affordable penalties in performance. Our goal is to do it, in addition, with the minimum impact in the architecture at hardware level.On the other hand, on focal-plane processors with a pixel-to-PE assignment, the area occupation is not only a matter of cost or h...

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Section: Validationmentioning

confidence: 86%

Split and shift methodology on cellular processor arrays: area saving versus time penalty

Fernandez

Brea

Cabello

2012

Circuit Theory & Apps

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“…Image processing being a parallel oriented operation due to the 2D image pixel grid nature, the use of a processor based on DT-CNN is a straight forward solution for an efficient and fast image processing operations. What is presented in this paper is the evolution of the implementation presented in [4], adapted to fit the specifications for a low cost, low power, small size robotic sensor device.…”

Section: Introductionmentioning

confidence: 99%

“…As shown in [4], binary images are enough for most of the pre-processing algorithms, as well as basic robot guiding algorithms. In [2] the 1-bit DT-CNN with full functionality was presented, and when compared with the 8-bit grey scale DT-CNN presented in [3] problems related with the truncation process yield to a complex correction system, which supports the utilization of the binary version.…”

Section: Introductionmentioning

confidence: 99%

High performance DT-CNN camera device design on ACTEL IGLOO low power FPGA

Consul-Pacareu

Albó-Canals

Vilasís-Cardona

et al. 2011

2011 20th European Conference on Circuit Theory and Design (ECCTD)

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In this paper we present a complete study on the balance between high performance image processing and low power consumption without using expensive components. Our proposal consists in implementing a Discrete Time Cellular Neural Network (DT-CNN) on a low power Actel IGLOO nano Field Programmable Gate Array (FPGA). This is a definitive step further from previous work to obtain an intelligent camera device for robots. Applications in Robot Guidance have rapidly increased in the last years as robots break in different fields of everyday live, which most of this robotic devices need sensors for navigation. Our proposed low cost solution avoids highly complex architectures, expensive smart sensors and low performance navigation systems.

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Robot guiding with obstacle avoidance algorithm for uncertain enviroments based on DTCNN

Cited by 2 publications

References 8 publications

Split and shift methodology on cellular processor arrays: area saving versus time penalty

Split and shift methodology on cellular processor arrays: area saving versus time penalty

High performance DT-CNN camera device design on ACTEL IGLOO low power FPGA

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