Risc-V Random Test Generator

Tran, Dai Duong; Truong, Thi Giang; Giang, Truong; Do, The Duc

doi:10.1109/acomp53746.2021.00027

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B Model-based Random Testing1

Evaluation a A Coverage Study1

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2024

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Cited by 2 publications

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“…For example, directed-random test-sequence generation has been used to debug pipeline and memory bugs, as well as to uncover unexpected divergences in implementation behavior [1], [13]. There exist multiple test generators for RISC-V, e.g., RISC-V RTG [14], but RISCV-DV 6 remains the most advanced such sequence generator for RISC-V, and it works well for these use cases, particularly where detailed traces can be compared. RISCV-DV generates assembly programs, ready to be converted to in-memory images for execution.…”

Section: B Model-based Random Testingmentioning

confidence: 99%

See 1 more Smart Citation

Randomized Testing of RISC-V CPUs Using Direct Instruction Injection

Joannou¹,

Woodruff²,

Fuchs³

et al. 2024

IEEE Des. Test

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Section: B Model-based Random Testingmentioning

confidence: 99%

“…We evaluated coverage of the RISC-V architecture using sailcov 13 , which measured how many branches of the RISC-V Sail model were explored during a run. We compared our TestRIG QCVEngine against the RISC-V test suite (riscvtests 14 ) and the RISCV-DV generator.…”

Section: Evaluation a A Coverage Studymentioning

confidence: 99%