RISC-V Online Tutor

Morgan, Frank; Beretta, Arthur; Gallivan, Ian; Clancy, Joseph; Rousseau, Frédéric; George, Roshan; Bakó, László; Callaly, Frank

doi:10.1007/978-3-030-82529-4_14

Cited by 2 publications

(2 citation statements)

References 2 publications

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“…Researchers can explore the scope of this approach within the Comp-Arch course, suggesting alternate approaches to cover diverse content, such as pipelining, while maintaining student motivation. Addressing potential tool-related difficulties, as noted by Omer, Farooq & Abid (2021) , researchers can introduce more user-friendly tools and assess their effects on students’ development, as exemplified by RISC-V Online Tutor ( Morgan et al, 2021 ). Furthermore, the study acknowledges the high workload placed on students by this approach.…”

Section: Discussionmentioning

confidence: 99%

“…According to a survey by Omer, Farooq & Abid (2021) survey tools are needed to have sufficient visualization to help students comprehend subjects. In their work, Morgan et al (2021) developed the RISC-156 V Online Tutor, which not only incorporates significant interaction signals within real hardware, sandboxes, knowledge checks, and challenges but also provides a RISC-V Integrated Development Environment (IDE) for assembly programming, as well as VHDL processor capture, simulation, and prototyping. RISC-V IDE for assembly programming, and VHDL processor capture, simulation, and prototyping.…”

Section: Related Workmentioning

confidence: 99%

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Teaching computer architecture by designing and simulating processors from their bits and bytes

Doğan,

Öztoprak,

Tolun

2024

PeerJ Computer Science

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Teaching computer architecture (Comp-Arch) courses in undergraduate curricula is becoming more of a challenge as most students prefer software-oriented courses. In some computer science/engineering departments, Comp-Arch courses are offered without the lab component due to resource constraints and differing pedagogical priorities. This article demonstrates how students working in teams are motivated to study the Comp-Arch course and how instructors can increase student motivation and knowledge by taking advantage of hands-on practices. The teams are asked to design and implement a 16-bit MIPS-like processor with constraints as a specific instruction set, and limited data and instruction memory. Student projects include following three phases, namely, design, desktop simulator implementation, and verification using hardware description language (HDL). In the design phase, teams develop their Comp-Arch to implement specified instructions. A range of designs resulted, e.g., (a) a processor with extensive user-defined instructions resulting in longer cycle times (b) a processor with a minimal instruction set but with a faster clock cycle time. Next, teams developed a desktop simulator in any programming language to execute instructions on the architecture. Finally, students engage in Verilog Hardware Description Language (HDL) projects to simulate and verify the data-path designed during the initial phase. Student feedback and their current understanding of the project were collected through a questionnaire featuring varying Likert scale questions, some with a ten-point scale, and others with a five-point scale. Results of the survey show that the hands-on approach increases students’ motivation and knowledge in the Comp-Arch course, which is centered around computer system design principles. This approach can also be effectively extended to related courses, such as Microprocessor Design, which delves into the intricacies of creating and implementing microprocessors or central processing units (CPUs) at the hardware level. Furthermore, the present study demonstrates that interactions, specifically through peer reviews and public presentations, between students in each phase increases their knowledge and perspective on designing custom processors.

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Section: Discussionmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%