Ripple: Profile-Guided Instruction Cache Replacement for Data Center Applications

Khan, Tanvir Ahmed; Zhang, Dexin; Sriraman, Akshitha; Devietti, Joseph; Pokam, Gilles; Litz, Heiner; Kasikci, Baris

doi:10.1109/isca52012.2021.00063

Cited by 15 publications

(7 citation statements)

References 72 publications

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“…Prior work from Google and Facebook shows that their widely-deployed data center applications lose more than 15% of all pipeline slots due to frontend stalls [25,27,67,133]. As these applications are proprietary, we use the applications used by prior work [75,77,78,86,100,138,150], where frontend stalls are similarly frequent (more than 15%) due to large instruction footprints. These applications include cassandra [2], kafka [3], and tomcat [4] from the Java DaCapo benchmark suite [31], drupal [142], wordpress [144], and mediawiki [143] from Facebook's OSS -performance benchmark suite [16], finagle-chirper and finagle-http [12] from the Java Renaissance benchmark suite [114], clang [6] while building LLVM [85], PostgreSQL [10] while serving pgbench [9] queries, Python [14] while running the pyperformance [11] benchmark suite, MySQL [146] while serving TPC-C queries [35], and verilator [13] while emulating the Rocket Chip [7].…”

Section: Experimental Methodologymentioning

confidence: 99%

“…As shown, none of the 13 applications we study significantly benefit from these existing replacement policies. Specifically, the state-of-the-art BTB replacement policy, GHRP does not perform well for applications with large working sets [78].…”

Section: Why Do Prior Replacement Policies Fall Short?mentioning

confidence: 99%

“…Moreover, they lose all the information about a branch every time the corresponding BTB entry is evicted. Since large working set sizes (both instruction and branch footprint) are the key characteristics of data center applications [27,67,75,77,78,132], it is necessary to retain branch reuse behavior even when the corresponding entry is not present in the BTB.…”

Section: Why Do Prior Replacement Policies Fall Short?mentioning

confidence: 99%

“…Thermometer collects the basic block execution trace using Intel PT [1]. Similar to prior work [78], Thermometer uses Intel PT due to its low runtime overhead (only up to 1% [69][70][71]151]) and widespread adoption in today's data centers [36,39]. Intel PT provides Thermometer with a trace of dynamically executed branch instructions.…”

Section: Profile Collectionmentioning

confidence: 99%

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Thermometer

Song

Khan

Shahri

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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Modern processors employ a decoupled frontend with Fetch Directed Instruction Prefetching (FDIP) to avoid frontend stalls in data center applications. However, the large branch footprint of data center applications precipitates frequent Branch Target Buffer (BTB) misses that prohibit FDIP from eliminating more than 40% of all frontend stalls. We find that the state-of-the-art BTB optimization techniques (e.g., BTB prefetching and replacement mechanisms) cannot eliminate these misses due to their inadequate understanding of branch reuse behavior in data center applications.In this paper, we first perform a comprehensive characterization of the branch behavior of data center applications, and determine that identifying optimal BTB replacement decisions requires considering both transient and holistic (i.e., across the entire execution) branch behavior. We then present Thermometer, a novel BTB replacement technique that realizes the holistic branch behavior via a profile-guided analysis. Based on the collected profile, Thermometer generates useful BTB replacement hints that the underlying hardware can leverage. We evaluate Thermometer using 13 widelyused data center applications and demonstrate that it provides an average speedup of 8.7% (0.4%-64.9%) while outperforming the state-of-the-art BTB replacement techniques by 5.6× (on average, the best performing prior work achieves 1.5% speedup). We also demonstrate that Thermometer achieves a performance speedup that is, on average, 83.6% of the speedup achieved by the optimal BTB replacement policy.

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Section: Experimental Methodologymentioning

confidence: 99%

Section: Why Do Prior Replacement Policies Fall Short?mentioning

confidence: 99%

Section: Why Do Prior Replacement Policies Fall Short?mentioning

confidence: 99%

Section: Profile Collectionmentioning

confidence: 99%

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Thermometer

Song

Khan

Shahri

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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“…For the last-level cache(LLC), [3] devised an extra storage based on the LRU policy, to represent the set-dueling counters and insertion and promotion vectors(IPVs), which achieves a weighted speedup of 6.2% over the LRU. In [4], an I-Cache (instruction cache) replacement algorithm is proposed based on the data center application mode that applies the idea of combining the replacement algorithm with instruction prefetching; it is implemented by software. Across different prefetching configurations, this method can avoid up to 53% of I-Cache misses.…”

Section: Introductionmentioning

confidence: 99%

Design of DMS-RRIP replacement algorithm for L1-cache of RISC-V-based single-core embedded processor

Ma,

Jiang,

et al. 2023

Second International Conference on Electronic Information Technology (EIT 2023)

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As a new open-source reduced instruction set, RISC-V has received a large amount of attention. Because of its highly concise instruction set encoding and modular extended instruction sets, RISC-V instruction set has been widely used in the embedded system [1]. As an indispensable part of the current embedded processor, cache directly affects the speed of the processor. In cache design, the cache replacement algorithm plays a key role, which is a necessary component affecting the hit rate of cache in. Aiming at the L1-Cache of RISC-V embedded processor, this paper proposes a cache replacement algorithm that dynamically adjusts the storage as per the memory access characteristics of the executing program. The simulation results show that the proposed replacement algorithm effectively improves the cache hit rate, and thus improves the overall performance of the processor.

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