Rigorous three-dimensional photoresist exposure and development simulation over nonplanar topography

Kirchauer, H.; Selberherr, S.

doi:10.1109/43.664225

Cited by 8 publications

(1 citation statement)

References 17 publications

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“…Although the numerical formulation does not rigorously simulate photoresist baking and development, the model nevertheless approximates well the effects of photoresist processing, giving excellent quantitative agreement between simulation and experimental data [40]. These modeling assumptions also improve the computation speed up to 3 orders of magnitude compared with rigorous photoresist models [41], [42].…”

Section: Lithography Optimizationmentioning

confidence: 79%

Level-specific lithography optimization for 1-Gb DRAM

Wong

Ferguson

Mansfield

et al. 2000

IEEE Trans. Semicond. Manufact.

103

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A general level-specific lithography optimization methodology is applied to the critical levels of a 1-Gb DRAM design at 175-and 150-nm ground rules. This three-step methodology-ruling out inapplicable approaches by physical principles, selecting promising techniques by simulation, and determining actual process window by experimentation-is based on process latitude quantification using the total window metric. The optimal lithography strategy is pattern specific, depending on the illumination configuration, pattern shape and size, mask technology, mask tone, and photoresist characteristics. These large numbers of lithography possibilities are efficiently evaluated by an accurate photoresist development bias model. Resolution enhancement techniques such as phase-shifting masks, annular illumination and optical proximity correction are essential in enlarging the inadequate process latitude of conventional lithography.

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Section: Lithography Optimizationmentioning

confidence: 79%