RF/wireless interconnect for inter- and intra-chip communications

Chang, Mau-Chung Frank; Roychowdhury, Vwani P.; Zhang, Jintao; Shin, Hyunchol; Qian, Yongxi

doi:10.1109/5.920578

Cited by 228 publications

(124 citation statements)

References 16 publications

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“…21 as a miniature wireless local area network (LAN) located inside a SIP (or a MCM) [7]. Like any other wireless communication system, this miniature LAN contains ULSI I/Os as users, capacitor couplers as near field antennas, RF transceivers and off-chip but in-package MTL (microwave transmission line) as a shared broadcasting medium.…”

Section: B Wireless Multicarrier Cdma-interconnect (Mccdma-i) For Sipmentioning

confidence: 99%

“…The future SIP interconnect systems would require wide bandwidth, short latency, real-time re-configurability and simultaneous multiI/O's service. To meet such system needs, we have developed a MCCDMA-I (multicarrier CDMA-Interconnect) by combining the FDMA-I and CDMA-I to take advantages from both systems [7], [9]. The MCCDMA-I can be connected in either wired (via direct-coupling) or wireless (via capacitor-coupling) fashion depending on specific system applications.…”

Section: B Wireless Multicarrier Cdma-interconnect (Mccdma-i) For Sipmentioning

confidence: 99%

“…For example, given a MCCDMA-I scheme with of 32 channels, of 4, and an aggregate data rate of 128 Gbps/pin, each I/O then will run at 1 Gbps. At this speed and with four codes, the correlator required for each I/O can be implemented in less than 1000 m while dissipating less than 1 mW in 65-nm CMOS technology [7], [28].…”

Section: System Benefitsmentioning

confidence: 99%

“…To overcome the limitations of traditional TDMA-I, a number of new interconnect schemes have been investigated recently to greatly increase the aggregate data rate and concurrency as well as to reduce latency and power consumption [7]- [13]. These new schemes permit the use of a combination of other multiple access techniques, namely code division multiple access (CDMA) and frequency division multiple access (FDMA).…”

Section: Introductionmentioning

confidence: 99%

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Advanced RF/Baseband Interconnect Schemes for Inter- and Intra-ULSI Communications

Chang

Verbauwhede

Chien

et al. 2005

IEEE Trans. Electron Devices

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Abstract-Future inter-and intra-ULSI interconnect systems demand extremely high data rates (up to 100 Gbps/pin or 20-Tbps aggregate) as well as bidirectional multiI/O concurrent service, re-configurable computing/processing architecture, and total compatibility with mainstream silicon system-on-chip and system-in-package technologies. In this paper, we review recent advances in interconnect schemes that promise to meet all of the above system requirements. Unlike traditional wired interconnects based solely on time-division multiple access for data transmission, these new interconnect schemes facilitate the use of additional multiple access techniques including code-division multiple access and frequency-division multiple access to greatly increase bandwidth and channel concurrency as well as to reduce channel latency. The physical transmission line is no longer limited to a direct-coupled metal wire. Rather, it can be accomplished via either wired or wireless mediums through capacitor couplers that reduce the baseband noise and dc power consumption while simplifying the fabrication process by eliminating vertical metal studs needed in three-dimensional ICs. These new advances in interconnect schemes would fundamentally alter the paradigm of ULSI data communications and enable the design of next-generation computing/processing systems.

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Section: B Wireless Multicarrier Cdma-interconnect (Mccdma-i) For Sipmentioning

confidence: 99%

Section: B Wireless Multicarrier Cdma-interconnect (Mccdma-i) For Sipmentioning

confidence: 99%

Section: System Benefitsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Advanced RF/Baseband Interconnect Schemes for Inter- and Intra-ULSI Communications

Chang

Verbauwhede

Chien

et al. 2005

IEEE Trans. Electron Devices

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“…As a result, metallic interconnection schemes are being gradually replaced by wireless inter-chip and intra-chip communication standards, overcoming the limitation of speed in the process [2][3][4]. A popular technique employed in on-chip * E-mail: apratimroy45@gmail.com integrated wireless systems is ultra-wideband transmission (UWB), with features of immunity to interference, gigabit transmission speed, minimal effective power density, small antenna dimensions and provision for spread spectrum multiple access [5,6].…”

Section: Introductionmentioning

confidence: 99%

A power efficient bandwidth regulation technique for a low-noise high-gain RF wideband amplifier

Roy

Rashid

2012

Open Engineering

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In this paper, a single-stage deep sub-micron wideband amplifier (LNA) using a reactive resonance tank and passive port-matching techniques is demonstrated operating in the microwave frequency range (K band). A novel power-efficient bandwidth (BW) regulation technique is proposed by incorporating a small impedance in the resonance tank of the amplifier configuration. It manifests a forward gain in the range of 5.9-10.7 dB covering a message bandwidth of 10.6-6.3 GHz. With regulation, input-output reflection parameters (S 11 , S 22 ) and noise figure can be manipulated by -12.7 dB, -22.7 dB and 0.36 dB, respectively. Symmetric regulation is achieved for bandwidth and small signal gain with respect to moderate tank impedance (36.5% and -26.8%, respectively) but the effect on noise contribution remains relatively low (increase of 7% from a base value of 2.39 dB). The regulated architecture, when analyzed with 90 nm silicon CMOS process, supports low power (9.1 mW) on-chip communication. The circuit is tested with a number of combinations for tank (drain) impedance to verify the efficiency of the proposed technique and achieves better figures of merit when compared with published literature.

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On‐Chip Surfing Interconnect

Yang¹,

Greenstreet²

2012

Advanced Circuits for Emerging Technologies

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With growing chip sizes and operating frequencies, on-chip global interconnect has become a critical bottleneck for CMOS technology. With processes scaling into deep submicron scales, the gap between gate delay and globalinterconnect delay increases with each technology generation. Bandwidth is also important for on-chip interconnect and is limited by skew and jitter. Due to temperature variation, crosstalk noise, power supply variation and parameter variation, timing variation increases with the length of global interconnect lines. Jitter and skew in the transmitter and receiver's clocks add timing variation to on-chip interconnect communication. Repeaters in a buffering technique amplify clock jitter and drop pulses due to intersymbol interference. Latches can be inserted in place of some of the buffers to control the timing variation. However, these latches increase latency and power consumption. In 2002, a novel circuit technique called "surfing" was proposed to bound the timing uncertainty in wave pipelines [57]. This thesis extends the application of surfing to on-chip interconnects and introduces surfing RC interconnect and surfing LC interconnect techniques. For RC interconnects, we present a jitter attenuating buffer. This buffer uses inverters with variable output strength to implement a simple, lowgain DLL. Chains of these surfing buffers attenuate jitter making them well suited for source-synchronous interconnect. Furthermore, our chains can be used to reliably transmit handshaking signals and support sliding-window protocols to improve the throughput of asynchronous communication. We use distributed varactors to dynamically vary the latency of LC interconnects and thus effect surfing. Different from RC signaling, signals on LC interconnect propagate at nearly the speed-of-light. The varactors not only modulate the line latency, but also sharpen the edges of signals. We present both a full-swing and a low-swing LC interconnect designs. In both interconnects, the jitter and skew are attenuated along the line due to the surfing effect. In the low swing interconnect, the surfing effect also helps to reshape the pulses to increase the eye height. To demonstrate these techniques in real silicon, we designed, fabricated and tested a chip. The testing Without extensive support, discussion and endless encouragement from Dr. Mark Greenstreet, this work would not have been possible. Most importantly, Dr. Mark Greenstreet tries every possible way to help me to enjoy this work and make my stay at Vancouver to be such a wonderful time. He and his family, Susan Greenstreet, Laura Greenstreet and Jenny Greenstreet impress me a lot by their sense of humor to the world. I would not have completed the chip design without the support and help from the member of VLSI research group in SUN Microsystems Laboratory. Special thanks goes to Dr. Robert Drost, who triggers the idea of varactors used in the surfing interconnect, Alex Chow for a lot of discussions on Varactors and line parameters and helps on chip testing, Justin...

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RF/wireless interconnect for inter- and intra-chip communications

Cited by 228 publications

References 16 publications

Advanced RF/Baseband Interconnect Schemes for Inter- and Intra-ULSI Communications

Advanced RF/Baseband Interconnect Schemes for Inter- and Intra-ULSI Communications

A power efficient bandwidth regulation technique for a low-noise high-gain RF wideband amplifier

On‐Chip Surfing Interconnect

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