RF Transceiver for the Multi-Mode Radar Applications

Ha, Jae Kwon; Noh, Chang Kyun; Lee, Jin Sub; Kang, Ho Jin; Kim, Yu Min; Kim, Tae Hyun; Jung, Ha Neul; Lee, Sang-Hwan; Cho, Choon Sik; Kim, Young Jin

doi:10.3390/s21051563

Cited by 4 publications

(4 citation statements)

References 19 publications

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“…To produce single-chip RF transceivers for 60 GHz wireless applications, a quadrature transceiver architecture is widely adopted. This is because 60 GHz wireless communication usually employs quadrature modulation and demodulation schemes such as quadrature amplitude modulation (QAM) to achieve a high data rate [4][5][6]. One of the challenges in designing a quadrature transceiver is the I/Q phase imbalance in the I/Q LO signals.…”

Section: Introductionmentioning

confidence: 99%

A 52-to-57 GHz CMOS Phase-Tunable Quadrature VCO Based on a Body Bias Control Technique

Lee

Shin

2023

Electronics

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This paper presents a 52-to-57 GHz CMOS quadrature voltage-controlled oscillator (QVCO) with a novel I/Q phase tuning technique based on a body bias control method. The QVCO employs an in-phase injection-coupling (IPIC) network comprising four diode-connected FETs for the quadrature phase generation. The I/Q phase error is calibrated by controlling the body bias voltage offset of the QVCO’s four core FETs. This technique effectively covers a wide range of I/Q phase error between −13.4° and +10.7°. It also minimally induces the unwanted variations in the phase noise, current dissipation, and oscillation frequency, which were found to be only 0.4 dB, 0.07%, and 36 MHz, respectively. After the IPIC-QVCO, a phase-tunable two-stage LO buffer employing a 3-bit switched-capacitor bank was added for additional phase tuning, leading to the extension of the phase tuning range up to −22.7–+20.0°. The proposed QVCO is implemented in a 40 nm RF CMOS process. The measured results show that the QVCO covers a frequency band from 52.4 to 57.6 GHz while consuming 26.2 mW. The phase noise and the figure-of-merit of the QVCO are −91.8 dBc/Hz at 1 MHz offset and −172.4 dBc/Hz, respectively. We also realized a fully integrated 55 GHz quadrature RF transmitter employing the phase-tunable QVCO and LO generator. The effectiveness of the proposed phase-tunable LO generator was confirmed by verifying the image rejection ratio (IRR) calibration at the RF output.

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Section: Introductionmentioning

confidence: 99%

A 52-to-57 GHz CMOS Phase-Tunable Quadrature VCO Based on a Body Bias Control Technique

Lee

Shin

2023

Electronics

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“…Recently, the demand for military or civilian drones and surveillance radars has been increasing. In radar transceivers, several forms of waves are used to determine object distance and velocity information, of which continuous wave (CW) and frequency modulated continuous wave (FMCW) are typically used [1][2][3]. If CW is used, the speed of the object can be determined but not the distance.…”

Section: Introductionmentioning

confidence: 99%

“…To solve this problem, FMCW and CW can be used together to verify the distance and speed information of multiple targets without a ghost target [2]. For CW, the Doppler frequency is added to the carrier frequency and received by the receiver, whereas for FMCW, the additional beat frequency, as well as the Doppler frequency, is received; therefore, for each case, the sampling rate required by the analog-to-digital converter (ADC) is different.…”

Section: Introductionmentioning

confidence: 99%

SAR ADC for a Multimode Radar Transceiver with Offset Calibration

Lee

Cho

et al. 2022

J Electromagn Eng Sci

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In this paper, we design a successive approximation register (SAR) analog-to-digital converter (ADC) suitable for multimode radar transceivers. For multimode radars, the sampling rate required by ADC varies according to the continuous wave (CW) or frequency modulated continuous wave (FMCW) used for operation. Therefore, depending on which waveform is used, the input is designed to enter two paths. For path 1, we obtained 9.23 bits of effective number of bits (ENOB), 57.35 dB of signal-to-noise distortion ratio (SNDR), and 64.62 dB of spurious free dynamic range (SFDR), and the power consumption was 0.3481 mW, resulting in a figure of merit (FOM) of 28.9 fJ/Conv-Step. On path 2, we obtained an 8.97 bit of ENOB, 55.76 dB of SNDR, and 60.53 dB of SFDR, and the power consumption was 1.72 μW, resulting in a FOM of 34.2 fJ/Conv-Step. Further, a circuit was constructed to reduce the offset of the comparator. As a result of 100 Monte Carlo simulations, the offset was reduced from -46 mV/+50 mV to -4 mV/+4 mV when the worst case was considered.

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“…First, advancements in semiconductor technology have enabled the integration of radio frequency (RF) front-end, baseband filtering, and data conversion systems on a single chip at competitive prices and reasonable performance levels [11,12]. Researchers developed a complementary metal-oxide-semiconductor (CMOS) Ku-band transceiver for frequency-modulated continuous-wave (FMCW) radar imaging [13,14], and in another study, they proposed an X-band CMOS four-channel phased array transceiver for synthetic aperture radar (SAR) imaging [15].…”

Section: Introductionmentioning

confidence: 99%

An X-Band CMOS Digital Phased Array Radar from Hardware to Software

Chou

et al. 2021

Sensors

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Phased array technology features rapid and directional scanning and has become a promising approach for remote sensing and wireless communication. In addition, element-level digitization has increased the feasibility of complicated signal processing and simultaneous multi-beamforming processes. However, the high cost and bulky characteristics of beam-steering systems have prevented their extensive application. In this paper, an X-band element-level digital phased array radar utilizing fully integrated complementary metal-oxide-semiconductor (CMOS) transceivers is proposed for achieving a low-cost and compact-size digital beamforming system. An 8–10 GHz transceiver system-on-chip (SoC) fabricated in 65 nm CMOS technology offers baseband filtering, frequency translation, and global clock synchronization through the proposed periodic pulse injection technique. A 16-element subarray module with an SoC integration, antenna-in-package, and tile array configuration achieves digital beamforming, back-end computing, and dc–dc conversion with a size of 317 × 149 × 74.6 mm3. A radar demonstrator with scalable subarray modules simultaneously realizes range sensing and azimuth recognition for pulsed radar configurations. Captured by the suggested software-defined pulsed radar, a complete range–azimuth figure with a 1 km maximum observation range can be displayed within 150 ms under the current implementation.

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RF Transceiver for the Multi-Mode Radar Applications

Cited by 4 publications

References 19 publications

A 52-to-57 GHz CMOS Phase-Tunable Quadrature VCO Based on a Body Bias Control Technique

A 52-to-57 GHz CMOS Phase-Tunable Quadrature VCO Based on a Body Bias Control Technique

SAR ADC for a Multimode Radar Transceiver with Offset Calibration

An X-Band CMOS Digital Phased Array Radar from Hardware to Software

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