RF characterization and isolation properties of mesoporous Si by on-chip coplanar waveguide measurements

Porous silicon for electrical isolation in radio frequency devices: A review

“…For example, the characterization of the substrate impact on the resistive losses of a RF circuit requires also an accurate evaluation of the losses within the metal lines. 80 Indeed, the two contributions cannot be separated, and none is negligible in comparison to the other when dealing with high performance substrates such as Porous Silicon. Therefore, the metal lines need to be meshed carefully, leading to a highly non-uniform discretization of space.…”

“…For the same PS layer thickness, Contopanagos et al has also shown an evolution of the silicon (6.85 XÁcm)/mesoporous silicon loss tangent ratio from 200 to 20 varying the frequency from 1 to 10 GHz. 80 Finally, Sarafis et al extracted AC conductivities from CPW measurements on PS layers with porosities between 70% and 80%. They estimated this value around 5Á10 À4 S/cm at 10 GHz.…”

Single photoresist masking for local porous Si formation

“…It is thus interesting to form porous Si layers on selected areas of the Si wafer in order to locally change the substrate properties for a number of different applications [3][4][5][6]. An increasing interest has recently been devoted to the dielectric [7,8] and thermal [9][10][11][12][13] properties of porous Si for its use as a local substrate on Si for the on-chip integration of RF passive devices [14][15][16][17][18] and thermal [19,20] or thermoelectric devices [21].…”

RF non-linearities from Si-based substrates

“…In this case, by creating a thick porous silicon (PSi) layer presenting an intrinsic highresistivity property, on-chip passive integration on standard-Si (std-Si) compatible with high thermal budget of Si CMOS process is achievable [3]- [4]. This technology leads to lower crosstalk at high frequencies (> 3 GHz) between the fabricated devices in SoC thanks to its lower permittivity (about one fourth) than std-Si [5]- [6]. On the other side, various Si-based substrates compatible with SOl CMOS process have been studied [2] such as High Resistivity Silicon (HR-Si) [7] , High Resistivity Silicon-on-Insulator (HR-SOI) [8] and Trap-Rich Silicon (TR-Si) [9].…”