Revisiting shared virtual memory systems for non-coherent memory-coupled cores

Lankes, Stefan; Reble, Pablo; Sinnen, Oliver; Clauss, Carsten

doi:10.1145/2141702.2141708

Cited by 7 publications

(3 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In the remainder of this section, the realization of the project MetalSVM – an SCC‐related shared virtual memory management system – and the aims to investigate the potential of SVMs for non‐coherent memory‐coupled multicore systems is presented, as it can also be found as a sketch in . MetalSVM is implemented in terms of a bare‐metal hypervisor and located within a virtualization layer between the SCC's hardware and the actual operating system.…”

Section: Shared‐memory Programming On the Sccmentioning

confidence: 99%

See 1 more Smart Citation

New system software for parallel programming models on the Intel SCC many‐core processor

Clauss

Lankes

Reble

et al. 2013

Concurrency and Computation

Self Cite

View full text Add to dashboard Cite

SUMMARYSince the beginning of the multicore era, parallel processing has become prevalent across the board. On a traditional multicore system, a single operating system manages all cores and schedules threads and processes among them, inherently supported by hardware-implemented cache coherence protocols. However, a further growth of the number of cores per system implies an increasing chip complexity, especially with respect to the cache coherence protocols. Therefore, a very attractive alternative for future many-core systems is to waive the hardware-based cache coherency and to introduce a software-oriented message-passing based architecture instead: a so-called Cluster-on-Chip architecture. Intel's Single-chip Cloud Computer (SCC), a many-core research processor with 48 non-coherent memory-coupled cores, is a very recent example for such a cluster-on-chip architecture. The SCC can be configured to run one operating system instance per core by partitioning the shared main memory in a strict manner. However, it is also possible to access the shared main memory in an unsplit and concurrent manner, provided that either the caches are disabled or the cache coherency is then ensured by software. In this article, we detail our experiences gained while developing low-level software for message-passing and shared-memory programming on the SCC. We present an SCC-customized MPI library (called SCC-MPICH) as well as a shared virtual memory system (called MetalSVM) for the SCC. In doing so, we evaluate the potential of both programming models and we show how these models can be improved especially with respect to the SCC's many-core architecture. Copyright

show abstract

Section: Shared‐memory Programming On the Sccmentioning

confidence: 99%

mentioning

confidence: 99%

New system software for parallel programming models on the Intel SCC many‐core processor

Clauss

Lankes

Reble

et al. 2013

Concurrency and Computation

Self Cite

View full text Add to dashboard Cite

show abstract

“…Although there are projects that aim to realize software-based cache coherency on the SCC [20], [21], the common way is to divide the offdie DRAM logically and in a strict manner into 48 private regions. That way, an exclusive usage of the private regions' cache lines is guaranteed, so that the caches can be enabled without the risk of any inconsistencies.…”

Section: B Software-level Viewmentioning

confidence: 99%

Mapping the PRAM model onto the Intel SCC many-core processor

Clauss

Lankes

Bemmerl

2012

2012 International Conference on High Performance Computing &Amp; Simulation (HPCS)

Self Cite

View full text Add to dashboard Cite

The Parallel Random Access Machine (PRAM) model describes an abstract register machine for analyzing the complexity and scalability of parallel algorithms. Unfortunately, it is not possible to implement this model directly in hardware but it is at least possible to emulate this abstract model on more realistic parallel machines. Moreover, the recent evolution of processor architectures towards a forthcoming many-core era seems to indicate that PRAM-derived hardware architectures may even become important in the near future. The Single-chip Cloud Computer (SCC) is a recent example for an experimental many-core processor. By means of this processor, researchers have the opportunity to investigate the requirements of tomorrow's software design and programming models. In this paper, we discuss if and how the PRAM model could be mapped onto the SCC by exploiting its many-core related hardware features.

show abstract