Revised Method for Extraction of the Thermal Resistance Applied to Bulk and SOI SiGe HBTs

Vanhoucke, T.; Boots, H. M. J.; Noort, W.D. van

doi:10.1109/led.2004.824242

Cited by 49 publications

(27 citation statements)

References 9 publications

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“…The thermal resistance of the device in our simulation is observed at ∼24 K/mW. This value is consistent with projections from the measurements of larger SOI bipolar devices in [14] and [15]. Due to the smaller dimensions of the simulated device and the thin-film materials, the thermal resistance value is higher than the measured thermal resistance of larger SOI bipolar devices.…”

Section: Device Structuresupporting

confidence: 88%

On the Performance of Lateral SiGe Heterojunction Bipolar Transistors With Partially Depleted Base

Raman

Sharma

Neogi

et al. 2015

IEEE Trans. Electron Devices

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This paper discusses improvements to a lateral bipolar device capable of integration into the existing CMOS process flow. With the help of simulations, we demonstrate that the emitter transit time limits the cutoff frequency of a lateral bipolar device. We show that with the introduction of a heterojunction and a partially depleted base, we can decrease the emitter transit time and increase the current gain and the cutoff frequency ( f t ) of the device. For a balanced design, our simulations indicate an n-p-n device with an f t of 812 GHz and an f max of 1.08 THz; and a p-n-p device with an f t of 635 GHz and an f max of 1.15 THz. The collector current at cutoff frequency for both n-p-n and p-n-p devices is ∼0.03 mA-roughly 100 times lower than commercial vertical heterojunction bipolar transistors.

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Section: Device Structuresupporting

confidence: 88%

On the Performance of Lateral SiGe Heterojunction Bipolar Transistors With Partially Depleted Base

Raman

Sharma

Neogi

et al. 2015

IEEE Trans. Electron Devices

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“…Dawson's technique [13], which again uses β or V BE as temperature-sensitive parameters, neglects the dependence of R TH on P D , and in the calibration phase, also that on T B (thus, being somewhat internally inconsistent). A modification of Dawson's technique proposed by Liu and Yuksel [14] allows the highlighting of some dependence of R TH on P D , but at the expense of neglecting that on T B , which is again inconsistent, while [15] and [16] introduce corrections to Dawson's results accounting for the effect of self-heating during the measurement, but still under a constant-R TH assumption. On the other hand, the technique introduced by Grossman et al [17] elaborates on Dawson's method, showing that assuming a linear dependence of R TH on the junction temperature leads to an exponential dependence of R TH on P D ; however, this technique also requires a separate calibration phase and nonstandard constant-I C measurements.…”

Section: Introductionmentioning

confidence: 99%

A new method to extract HBT thermal resistance and its temperature and power dependence

Menozzi

Barrett

Ersland

2005

IEEE Trans. Device Mater. Relib.

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This paper introduces a new technique for the measurement of the thermal resistance of HBTs. The method is very simple, because it requires only standard dc I C -V CE measurements taken at different baseplate temperatures, but it is able to account for the dependence of the thermal resistance on both the baseplate temperature and the dissipated power (under the simplifying assumption that the thermal resistance increases linearly with the dissipated power). We have obtained and shown consistent results extracted from devices with an emitter area ranging from 90 µm 2 (1 finger) to 1080 µm 2 (12 fingers). The thermal-resistance values extracted with a standard and wellknown technique are seen to fall inside the range of our results. We have also applied an alternative method that assumes a linear dependence between thermal resistance and junction temperature, and we have shown that both models lead to similar results, which points to the consistency and robustness of our extraction technique.

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“…Wafers were inserted into the chamber of an AET addax RX Rapid Thermal Annealer, which can accurately control the annealing temperature, duration, and the ambient gas mixture inside the chamber. Device thermal resistance used in this work was extracted and reported in [4] by correlating the junction temperature with dissipated power [9]. …”

Section: Devices and Test Conditionsmentioning

confidence: 99%

Understanding Radiation- and Hot Carrier-Induced Damage Processes in SiGe HBTs Using Mixed-Mode Electrical Stress

Cheng

Jun²,

Sutton³

et al. 2007

IEEE Trans. Nucl. Sci.

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Using mixed-mode annealing to help evaluate the responses of modern bipolar transistors, we compare the damage processes associated with X-ray irradiation-induced and hot carrier-induced damage in SiGe HBTs. Stress and radiation measurements indicate that the by-products of both X-ray irradiation-induced and hot carrier-induced trap reactions are identical. We use calculations to better understand the operative damage mechanisms, and find that a hydrogen reaction-diffusion model can predict the observed characteristics of our measurements. Calculations indicate that the transport of hydrogen molecules inside the emitter-base oxides determines the trap generation and recovery processes.

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Revised Method for Extraction of the Thermal Resistance Applied to Bulk and SOI SiGe HBTs

Cited by 49 publications

References 9 publications

On the Performance of Lateral SiGe Heterojunction Bipolar Transistors With Partially Depleted Base

On the Performance of Lateral SiGe Heterojunction Bipolar Transistors With Partially Depleted Base

A new method to extract HBT thermal resistance and its temperature and power dependence

Understanding Radiation- and Hot Carrier-Induced Damage Processes in SiGe HBTs Using Mixed-Mode Electrical Stress

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