Review on Arbiter Physical Unclonable Function and its Implementation in FPGA for IoT Security Applications

Shariffuddin, Sk.; Sivamangai, N. M.; Napolean, A.; Naveenkumar, R; Kamalnath, S; Saranya, G

doi:10.1109/icdcs54290.2022.9780766

Cited by 6 publications

(4 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Chen et al [8] have proposed a secure wireless transmission scheme for smart grid IoT. The second aspect involves exploring the security concerns of PIoT by incorporating physical layer security (PLS) measures [9]. Wang et al [10] have investigated the generation of physical layer keys for a new type of power system based on wireless channel characteristics.…”

Section: Related Workmentioning

confidence: 99%

Covert communication in power Internet of Things

Li,

Zhao,

Zhu

et al. 2024

Third International Conference on High Performance Computing and Communication Engineering (HPCCE 2023)

View full text Add to dashboard Cite

Section: Related Workmentioning

confidence: 99%

Covert communication in power Internet of Things

Li,

Zhao,

Zhu

et al. 2024

Third International Conference on High Performance Computing and Communication Engineering (HPCCE 2023)

View full text Add to dashboard Cite

“…The typical structure of the APUF is shown in the top-left panel of Fig. 1, which consists of n stages of multiplexer (MUX) pairs and an arbiter [17]. The challenge of the APUF is to determine the trigger signal transmission method in each MUX pair (a total of 24 transistors).…”

Section: Theoretical Foundationmentioning

confidence: 99%

PN-APUF: A MOSFET threshold loss based strong arbiter PUF with double-edge sampling

Shao,

Ma,

et al. 2024

IEICE Electron. Express

View full text Add to dashboard Cite

Arbiter physically unclonable function (APUF) is one of the most representative strong PUFs. Improving traditional APUF can enhance the performance of APUF-based PUFs. Accordingly, based on the theoretical foundation of traditional APUF, this paper proposes a novel PUF that utilizes the threshold loss, in which the PMOS transmits at a low level and the NMOS transmits at a high level, as the deviation source. In this manner, we significantly extended the delay deviation of both the rising and falling edges, thereby improving the randomness of PUF. The proposed PUF passed six subtests of the NIST randomness test suite. The delay unit only uses 20 minimum-size transistors with a fully custom layout area of 6.14 μm 2 in the TSMC 65-nm process, reducing the area by 15% compared to traditional APUF. The core area feature size is 93,018 F 2 which is more than sixfold reduction to the voltage-based PUFs. Furthermore, the proposed PUF generates twice the number of challenge-response pairs by sampling the rising and falling edges. It also exhibits a superior resistance against machine learning attacks compared to APUF, making it a better alternative.

show abstract

“…The arbiter PUF's goal is to consciously induce a race condition between two silicon chip digital paths. It consists of two chains of switch blocks (multiplexers) representing the two delay pathways, with an arbiter block at the conclusion of each chain [46][47][48]. According to Figure 7, the switch block can be in one of two configurations, straight if the challenge bit is 0, or crossing if it is 1.…”

Section: Delay-based Pufsmentioning

confidence: 99%

FPGA-Based PUF Designs: A Comprehensive Review and Comparative Analysis

Lata,

Cenkeramaddi

2023

Cryptography

View full text Add to dashboard Cite

Field-programmable gate arrays (FPGAs) have firmly established themselves as dynamic platforms for the implementation of physical unclonable functions (PUFs). Their intrinsic reconfigurability and profound implications for enhancing hardware security make them an invaluable asset in this realm. This groundbreaking study not only dives deep into the universe of FPGA-based PUF designs but also offers a comprehensive overview coupled with a discerning comparative analysis. PUFs are the bedrock of device authentication and key generation and the fortification of secure cryptographic protocols. Unleashing the potential of FPGA technology expands the horizons of PUF integration across diverse hardware systems. We set out to understand the fundamental ideas behind PUF and how crucially important it is to current security paradigms. Different FPGA-based PUF solutions, including static, dynamic, and hybrid systems, are closely examined. Each design paradigm is painstakingly examined to reveal its special qualities, functional nuances, and weaknesses. We closely assess a variety of performance metrics, including those related to distinctiveness, reliability, and resilience against hostile threats. We compare various FPGA-based PUF systems against one another to expose their unique advantages and disadvantages. This study provides system designers and security professionals with the crucial information they need to choose the best PUF design for their particular applications. Our paper provides a comprehensive view of the functionality, security capabilities, and prospective applications of FPGA-based PUF systems. The depth of knowledge gained from this research advances the field of hardware security, enabling security practitioners, researchers, and designers to make wise decisions when deciding on and implementing FPGA-based PUF solutions.

show abstract

Review on Arbiter Physical Unclonable Function and its Implementation in FPGA for IoT Security Applications

Cited by 6 publications

References 19 publications

Covert communication in power Internet of Things

Covert communication in power Internet of Things

PN-APUF: A MOSFET threshold loss based strong arbiter PUF with double-edge sampling

FPGA-Based PUF Designs: A Comprehensive Review and Comparative Analysis

Contact Info

Product

Resources

About