Reversible logic issues in adiabatic CMOS

Abstract-Adiabatic logic is architecture design style which seems to be a good candidate to reduce the power consumption of digital cores. One key difference is that the power supply is also the clock signal. A lot of work on different adiabatic logic families has been done but the impact of the power supply and the powerclock network still remains to be studied. In this paper, we investigate the power-clock network effect on adiabatic energy dissipation. We derive closed-form analytical formulas to represent the output signal voltage and energy dissipation while taking into account the parasitic impedance of the power-clock network with respect to switching frequency such that adiabatic conditions are still met. Experiments, based on simulation, show that the power-clock network impacts both the energy efficiency of the circuit and its frequency.

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“…Finally, the capacitor is fully discharged during the waiting time. Using (6) and VC(T3) = VRECF, VC is determined as:…”

Section: ) Waiting Phasementioning

confidence: 99%

“…These devices introduce non-adiabatic losses which detriment overall energy efficiency of adiabatic logic. Additionally, frequency achieved in adiabatic circuits is far lower than in conventional CMOS logic [6,7].…”

Section: Introductionmentioning

confidence: 98%

Investigation of the power-clock network impact on adiabatic logic

Jeanniot

Todri‐Sanial

Nouet

et al. 2016

2016 IEEE 20th Workshop on Signal and Power Integrity (SPI)

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“…Considerable research is ongoing to construct adiabatic logic devices [8][9][10][11][12][13]. Advances in this technology will reduce the amount of heat that computing circuits dissipate and that should simplify their packaging and reliability.…”

Section: Energy and Information Flowsmentioning

confidence: 99%

Exploring a Theory Describing the Physics of Information Systems, a Physical Model of the Behavior of Information Systems

Harmon¹

2001

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Public reporting burden lor this collection of information is estimated to average t hour per response, including the time lor reviewing instructions AUTHOR(S)Scott Young Harmon PERFORMING ORGANIZATION NAMEIS) AND ADDRESS(ES)Zetetix PO Box 2640 Agoura CA 91376-2640 S. SPONSORING/MONITORING AGENCY NAME(S) AND ADDRESS(ES)Defense This project accomplished all of its objectives: document a theory of information physics, conduct a workshop on planning experiments to test this theory, and design experiments that validate this theory. Information physics proposes quantitative relationships between observable information flows and changes in the content information systems maintain. This theory explains all flows within information systems as either diffusive or force-driven. The forces driving information flows arise from the existence of goal content. The workshop participants discussed various theories and considered experiments that characterize the macroscopic phenomena underlying complex information system behavior. These participants identified experimental opportunities that exploit existing databases, execute simulations and conduct traditional controlled experiments. They recommended that focussed experiments to test theories explaining information system phenomena were feasible today. The experiment plan builds upon the workshop's result and proposes experiments that measure information device energy dissipation, test the independence of symbol execution work from device efficiency, measure information diffusion rates in information systems, and measure force-driven information flows. These experiments are both technically and programmatically feasible. When validated, the proposed theory can guide designers to reliably build more effective, secure and predictable information systems. SUBJECT TERMS

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“…Thus, any development in this domain can be directly applied to future technologies. Finally, the use of reversible circuits is already found in low power CMOS designs, adiabatic circuits [4,5], cryptography [6], optical computing [7] and digital signal processing [8,9] requiring that all the information encoded in the inputs be preserved in outputs.…”

Section: Introductionmentioning

confidence: 99%

Reversible Architecture of Computer Arithmetic

Sultana¹,

Radecka²

2014

IJCA

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Reversible logic plays an important role in emerging low power designs and quantum computing. This paper presents an efficient way to realize reversible arithmetic circuits especially targeting toward reversible arithmetic logic unit (RALU). In literature for reversible logic, not a significant advancement is found in integrating both logical and arithmetical functions, commonly known as arithmetic logic unit (ALU), a key feature of any computing system architecture. Here, this work presents a novel reversible arithmetic logic unit (ALU) performing basic functions similar to classical ALU such as addition, subtraction, AND, OR and XOR operations. Additional functions such as, NAND, NOR, XNOR and logical functions with single input inverted, overflow detection and comparison can also be performed with this design. The integration of these operations in single module using less number of control signals is not available in any of existing approaches. The design and analysis based on different parameters of reversible circuits -number of gates, garbage bits and quantum cost as well as simulation results are presented here. The proposed design offers efficient programmability and more flexibility than other methods. General TermsArithmetic design and logic structures.

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Reversible logic issues in adiabatic CMOS

Cited by 60 publications

References 6 publications

Investigation of the power-clock network impact on adiabatic logic

Investigation of the power-clock network impact on adiabatic logic

Exploring a Theory Describing the Physics of Information Systems, a Physical Model of the Behavior of Information Systems

Reversible Architecture of Computer Arithmetic

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