Reversible Implementation of Densely-Packed-Decimal Converter to and from Binary-Coded-Decimal Format Using in IEEE-754R

Kaivani, Amir; Alhosseini, A.Z.; Gorgin, Saeid; Fazlali, Mahmood

doi:10.1109/icit.2006.78

Cited by 4 publications

(14 citation statements)

References 16 publications

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“…The performance parameters, such as the gate count (GC), CI, GO, and QC, is summarized for each of the two proposed designs and are verified using the RCViewer+ tool [12]. The proposed designs compared with the existing design [7] found in the technical literature are shown in Table 2. The gate counts (GCs), CIs, and GOs of the proposed design 1 of B2DE are 27, 27, and 29, respectively, and that of the proposed design 2 of B2DE is 29, 29, and 31, respectively.…”

Section: Results Analysis and Discussionmentioning

confidence: 99%

“…The gate counts (GCs), CIs, and GOs of the proposed design 1 of B2DE are 27, 27, and 29, respectively, and that of the proposed design 2 of B2DE is 29, 29, and 31, respectively. The encoder's existing design by Kaivani et al [7] engaged 22, 22, and 24 of GCs, CIs, and GOs, respectively. There is an increase of 5 units and 7 units in the proposed design 1 and design 2 of encoder compared with the encoder design of Kaivani et al [7] in the three (GC, CI, and GO) parameters, as shown in Table 2.…”

Section: Results Analysis and Discussionmentioning

confidence: 99%

“…Reversible implementation of arithmetics circuits such as reversible adder and reversible multiplier [5][6] has gained interest over the last decades, where low power designs are achievable. In 2006, an approach for the reversible implementation of DPD encoder and decoder from and to BCD was proposed [7], where they use two reversible gates, namely, Feynman gate (FG) [8] and Toffoli gate (TG) [9]. However, both the design approaches (for encoder and decoder) possess a higher quantum cost (QC) of 199 and 612, respectively.…”

Section: Introductionmentioning

confidence: 99%

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Reducing Quantum Cost for Reversible Realization of Densely-packed-decimal Converters

Thabah

Saha

2021

IJE

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Section: Results Analysis and Discussionmentioning

confidence: 99%

Section: Results Analysis and Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Reducing Quantum Cost for Reversible Realization of Densely-packed-decimal Converters

Thabah

Saha

2021

IJE

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“…All the research papers consulted in this research [5,[19][20][21]. [3][4][14][15]18,[21][22][23][24][28][29] did not provide direct relationship between the width of fraction and the width of available unsigned registers in determining the upper bound of accuracy of decimal fraction computed within binary floating-point. We establish the direct relation-ships between y fraction bits and z bit of unsigned integral registers in the statement (8) and (9) On the reverse direction z bit unsigned integral register will be capable of representing decimal-digits fraction accurately without sophisticated algorithm.…”

Section: Resultsmentioning

confidence: 99%

Are Ieee 754 32-Bit and 64-Bit Binary Floating-Point Accurate Enough?

Hutabarat¹,

Purnama²,

Hariadi³

et al. 2011

MST

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This paper describes a research toward the accuracy of floating-point values, and effort to reveal the real accuracy. The methods used in this research paper are assignment of values, assignment of value of arithmetic expressions, and output the values using floating-point value format that helps reveal the accuracy. The programming-tool used are Visual C# 9, Visual C++ 9, Java 5, and Visual BASIC 9. These tools run on top of Intel 80 x 86 hardware. The results show that 1*10 -x cannot be accurately represented, and the approximate accuracy ranges only from 7 to 16 decimal digits.

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“…9). The same approach can be applied to design a reversible AND gate by letting the last input be '0' [11].…”

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confidence: 93%

The Design of Reversible BCD Digit Adders: Decreasing the Depth of Circuit

Naderpour

Vafaei

2008

2008 International Symposium on Communications and Information Technologies

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Reversible circuits, nowadays, have found grounds * Depth: The number of l1x or 2x2 reversible gates in many applications such as low power CMOS design and which are in the longest path from input to output. quantum computing. In reversible circuit design, decreasing Reduction of these three parameters simultaneously is three parameters is of interest: quantum cost, depth of the circuit difficult. Therefore, one or two of them are usually opted as and the number of garbage outputs. On the other hand, recently, .' . t t decimal computer arithmetic, for the sake of its preciseness, gains the main parameter for minimization and try to reduce others popularity. Given that the BCD digit adder is the basic unit in as much as possible. In this paper a new method for designing decimal arithmetic, in this paper we propose a new reversible reversible circuits, with the aim of minimizing the depth of the design for this unit with the aim of minimizing the depth of the circuit is proposed and applied to the reversible one digit circuit. Furthermore, we show that the proposed designing BCD adder. Since depth in reversible circuits can be method can be applied to any other reversible circuit for considered as the latency in classic circuits, the proposed reaching the minimum depth.adder is based on Carry-Look-Ahead (CLA) topology which has been proved to be the fastest [5]. The rest of paper is organized as follows: reversible gates Power dissipation is one of the important considerations in are explained in section 2; the prerequisites of BCD adders digital circuit design. A part of this energy loss is due to are discussed in section 3 while in section 4 the proposed switches and materials. The other part arises from Landauer's design is presented; section 5 compares the new design with principle [1] where he proved that in irreversible circuits previous works and finally section 6 summarizes the outcome losing one bit of information dissipates KT.Ln2 joules of heat of this paper. energy, where K is the Boltzmann's constant and T is the absolute temperature. Although the amount of dissipating heat II. REVERSIBLE GATES for room temperature is small, it can not be neglected in someAn n x n reversible circuit consists of n inputs and n applications (e.g. quantum circuit design). Furthermore, outputs with mapping of each input assignment to a unique Bennett [2] showed that reversible circuits do not lose output assignent and vice versa. There are two main types of information due to the one-to-one mapping between inputs reversible gates: Toffoli [6] and Fredkin [7]. An n-bit Toffoli and outputs; hence no extra energy loss, gate passes the first (n-1) inputs to output unaltered (as controlIn the design of reversible circuits two restrictions should signals) and for the last output the nth input inverts (as target be considered: signal) if all previous (n-1) signals are '1'.

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Reversible Implementation of Densely-Packed-Decimal Converter to and from Binary-Coded-Decimal Format Using in IEEE-754R

Cited by 4 publications

References 16 publications

Reducing Quantum Cost for Reversible Realization of Densely-packed-decimal Converters

Reducing Quantum Cost for Reversible Realization of Densely-packed-decimal Converters

Are Ieee 754 32-Bit and 64-Bit Binary Floating-Point Accurate Enough?

The Design of Reversible BCD Digit Adders: Decreasing the Depth of Circuit

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