Reversible Arithmetic Processor Using Quantum Dot Cellular Automata

Abstract

Quantum dot Cellular Automata (QCA) may be viewed as the potential digital logic design alternative to supplant the current CMOS Technology. The logical design is based on the polarization of electrons to transfer information which results in a huge improved performance metric in terms of speed, power & area. This paper focuses on the design of a Reversible Arithmetic Processor (RAP) with Reversible Multiplexer (RM) and Reversible Functional Gate (RFG) in QCA. The QCA Designer-E simulation tool has been used to design and verify all the proposed architecture and the energy dissipation has been simulated using a coherent vector energy engine setup. The total and average energy dissipation per cycle of our proposed RAP using QCA are 3 . 9 1 × 1 0 − 1 ev and 3 . 5 6 × 1 0 − 2 ev respectively. Regarding cell count, area, latency, and energy dissipation, the proposed architecture beats out the existing architecture.