Reverse pillar—a self-aligned and self- planarised metallisation scheme for submicron technology

Yeh, Jwu‐Lai; Hills, G.W.; Cochran, W. L.; Rana, V.; Garcia, AM

doi:10.1016/0042-207x(88)90470-8

Cited by 7 publications

(4 citation statements)

References 2 publications

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“…On the other hand, the Hall mobility minimum often observed in polysilicon with an intermediate doping level can hardly be explained by the segregation model only. The presence of a minimum in the mobility vs. doping concentration diagram was explained in terms of carrier trapping at grain boundaries (grain boundary trapping model) (3,4). It has been reported that the microstructure of polysilicon films depends on the deposition and annealing temperatures (5), dopant concentration (6), and film thickness (7).…”

Section: Discussionmentioning

confidence: 99%

“…3, is shown a schematic of the key components of the polish technique. The wafer (i) is placed in a holder (2) with the wafer surface in direct contact with a pad-covered table (4). During the polish experiment, the abrasive slurry (3) flows onto the surface of the pad and the rotation speed of the table and of the holder can be independently varied.…”

Section: Methodsmentioning

confidence: 99%

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Chemical‐Mechanical Polishing for Fabricating Patterned W Metal Features as Chip Interconnects

Kaufman

Thompson

Broadie

et al. 1991

J. Electrochem. Soc.

515

255

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Interconnect features of W metal, recessed in an SiO2 dielectric, can be formed using a novel chemical‐mechanical polish process. Mechanical action, to continually disrupt a surface passivating film on W, and chemical action, to remove W, appear to be requirements for workability of the process. A trial process chemistry using a ferricyanide etchant is described. Removal of the W is discussed in terms of competition between an etching reaction which dissolves W and a passivation reaction to reform WO3 on the surface of the W. This novel processing technology is compared with earlier methods of fabricating metal interconnect structures.

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Section: Discussionmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

Chemical‐Mechanical Polishing for Fabricating Patterned W Metal Features as Chip Interconnects

Kaufman

Thompson

Broadie

et al. 1991

J. Electrochem. Soc.

515

255

View full text Add to dashboard Cite

show abstract

“…The use of chemical mechanical polishing (CMP) in the semiconductor industry has grown rapidly since its invention in 1984 [10], particularly after the development of the copper metallization in very large scale integration (VLSI). This planarization technology has the advantage of eliminating step coverage between interconnect levels in the VLSI technology [11] via dielectric planarization or recessed metal planarization [12,13]. Tungsten CMP, in particular, is a well-researched and established process in this industry [13,14] In this work a one-step lithography process has been developed for molybdenum (Mo) and tungsten (W) CMP burying electrodes into an aluminium nitride (AlN) surface for use in electroacoustic devices.…”

Section: Introductionmentioning

confidence: 99%

Buried electrode electroacoustic technology for the fabrication of thin film based resonant components

Martin

Yantchev

Katardjiev

2006

J. Micromech. Microeng.

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A fabrication process for thin film electroacoustic devices utilizing buried electrodes is presented. A one-step lithography process has been developed to bury electrodes resulting in a planarized surface. The proposed technology is expected to bring about a number of benefits concerning the performance of a variety of thin film electroacoustic devices. With respect to thin film plate acoustic resonators (FPAR), burying the reflector electrodes results in improved reflectivity and potentially lower susceptibility to acousto-migration effects. It is also shown that employing the proposed technology for the fabrication of both thin film bulk acoustic resonators (FBAR) and thin film solidity mounted bulk acoustic resonators (SBAR) eliminates certain macro-structural defects in the piezoelectric film which is a prerequisite for substantially improved device performance and higher power handling capability. The buried electrode electroacoustic (EA) technology is demonstrated for a thin aluminium nitride (AlN) piezoelectric film with electrodes of both molybdenum (Mo) and tungsten (W). The latter have been primarily chosen because of their high electroacoustic material quality. Thin film resonant structures produced by this technology are characterized and their features are discussed.

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“…The CMP has been used in the microelectronic industry as a major planarization process step in making chips since the 1980s (92)(93)(94)(95). It generates a super smooth surface with an average roughness of less than 10 Å across a 300 mm wafer.…”

Section: Introductionmentioning

confidence: 99%

Interfacial Forces in Chemical-Mechanical Polishing

Liang

2009

Advanced Tribology

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The demand for microelectronic device miniaturization requires new concepts and technology improvement in the integrated circuits fabrication. In last two decades, Chemical-Mechanical Polishing (CMP) has emerged as the process of choice for planarization. The process takes place at the interface of a substrate, a polishing pad, and an abrasive containing slurry. This synergetic process involves several forces in multilength scales and multi-mechanisms. This research contributes fundamental understanding of surface and interface sciences of microelectronic materials with three major objectives. In order to extend the industrial impact of this research, the chemical-mechanical polishing (CMP) is used as a model system for this study. The first objective of this research is to investigate the interfacial forces in the CMP system. For the first time, the interfacial forces are discussed systematically and comparatively so that key forces in CMP can be pinpointed. The second objective of this research is to understand the basic principles of lubrication, i.e., fluid drag force that can be used to monitor, evaluate, and optimize CMP processes. New parameters were introduced to include the change of material properties during CMP. Using the experimental results, a new equation was developed to understand the principle of lubrication behind the CMP. The third objective is to study the synergy of those interfacial forces with electrochemistry. The electro-chemical-mechanical polishing (ECMP) of copper was studied. Experiments were conducted on the tribometer in combination with a potentiostat. Friction coefficient was used to monitor the polishing process and correlated with the wear behavior of post-CMP samples. Surface characterization was performed using AFM, SEM, and XPS techniques. Results from experiments were used to generate a new wear model, which provided insight from CMP iv mechanisms. The ECMP is currently the newest technique used in the semiconductor industries. This research is expected to contribute to the CMP technology and improve its process performance. This dissertation consists of six chapters. The first chapter covers the introduction and background information of surface forces and CMP. The motivation and objectives are discussed in the second chapter. The three major objectives which include approaches and expected results are covered in the next three chapters. Finally chapter VI summarizes the major discovery in this research and provides some recommendations for future work. v DEDICATION To my mother, for her unconditional love, affection and support. vi ACKNOWLEDGEMENTS First and foremost, I would like to express my deepest gratitude to my academic advisor, Dr. Hong Liang. She taught me how to become a good researcher and provided an independent environment to assist my growth. She also gave me countless supports and encouragements during my last four years of study at Texas A&M University. I also want to thank her for her great patience and invaluable directions in the preparation of this dis...

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Reverse pillar—a self-aligned and self- planarised metallisation scheme for submicron technology

Cited by 7 publications

References 2 publications

Chemical‐Mechanical Polishing for Fabricating Patterned W Metal Features as Chip Interconnects

Chemical‐Mechanical Polishing for Fabricating Patterned W Metal Features as Chip Interconnects

Buried electrode electroacoustic technology for the fabrication of thin film based resonant components

Interfacial Forces in Chemical-Mechanical Polishing

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