Revec: program rejuvenation through revectorization

Mendis, Charith; Jain, Ajay N.; Jain, Paras; Amarasinghe, Saman

doi:10.1145/3302516.3307357

Cited by 13 publications

(7 citation statements)

References 29 publications

(34 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The scheme examines the program control-flow graph (CFG) to detect and avoid SIMT deadlocks, where the execution of threads in a SIMT architecture becomes stalled or blocked, waiting for each other to release resources and preventing forward progress. Revec [164] is a transparent compiler optimization pass happening at the compiler IR level to rewrite old vectorized code using new vector instructions. It enables the performance portability of hand-vectorized code and execution portability across newer SIMD extension generations.…”

Section: ) Static Compile-time Approachmentioning

confidence: 99%

MIMD Programs Execution Support on SIMD Machines: A Holistic Survey

Mustafa,

Alkhasawneh,

Obeidat

et al. 2024

IEEE Access

View full text Add to dashboard Cite

The Single Instruction Multiple Data (SIMD) architecture, supported by various highperformance computing platforms, efficiently utilizes data-level parallelism. The SIMD model is used in traditional CPUs, dedicated vector systems, and accelerators such as GPUs, vector extensions, and Xeon Phi. It provides performance throughput in computation-intensive and data-parallel applications. Despite the similarity of data-processing principles between these architectures, porting various programming models between the reviewed platforms is challenging. Furthermore, enhancing the programmability of these architectures is an important feature for utilizing their emerging computing power and simplifying programming complexity. This paper reviews the basic principles of optimization techniques to run asynchronous Multiple Instruction Multiple Data (MIMD) on SIMD accelerators. It also surveys several GPU programming paradigms and application programming interfaces (APIs) and classifies these frameworks into different groups based on their criteria. In addition, a review of studies that performed a comparison of the collaborative execution of GPUs with CPUs and Xeon Phi is presented in this paper. This study will be beneficial for developers and researchers in the field of computer architecture and parallel computing of intensive scientific applications, specifically for early-stage high-performance computing researchers, to obtain a brief overview of performance optimization opportunities as well as the challenges of existing SIMD platforms.

show abstract

Section: ) Static Compile-time Approachmentioning

confidence: 99%

MIMD Programs Execution Support on SIMD Machines: A Holistic Survey

Mustafa,

Alkhasawneh,

Obeidat

et al. 2024

IEEE Access

View full text Add to dashboard Cite

show abstract

“…Additionally, authors have employed reinforcement learning (RL) in various works. Mendis et al [32] investigate transforming the integer linear programming solver into a graph neural network-based policy for auto-generating vectorization schemes. Also, domain-specific compilers such as COMET [33], JAX [34], and NWChem [35] are under active research for optimizing program execution.…”

Section: Machine Learning-based Autotunersmentioning

confidence: 99%

Cross-Feature Transfer Learning for Efficient Tensor Program Generation

Verma,

Raskar,

Emani

et al. 2024

Applied Sciences

View full text Add to dashboard Cite

Tuning tensor program generation involves navigating a vast search space to find optimal program transformations and measurements for a program on the target hardware. The complexity of this process is further amplified by the exponential combinations of transformations, especially in heterogeneous environments. This research addresses these challenges by introducing a novel approach that learns the joint neural network and hardware features space, facilitating knowledge transfer to new, unseen target hardware. A comprehensive analysis is conducted on the existing state-of-the-art dataset, TenSet, including a thorough examination of test split strategies and the proposal of methodologies for dataset pruning. Leveraging an attention-inspired technique, we tailor the tuning of tensor programs to embed both neural network and hardware-specific features. Notably, our approach substantially reduces the dataset size by up to 53% compared to the baseline without compromising Pairwise Comparison Accuracy (PCA). Furthermore, our proposed methodology demonstrates competitive or improved mean inference times with only 25–40% of the baseline tuning time across various networks and target hardware. The attention-based tuner can effectively utilize schedules learned from previous hardware program measurements to optimize tensor program tuning on previously unseen hardware, achieving a top-5 accuracy exceeding 90%. This research introduces a significant advancement in autotuning tensor program generation, addressing the complexities associated with heterogeneous environments and showcasing promising results regarding efficiency and accuracy.

show abstract

“…Vectorization methods for loops include SLP-oriented loop unrolling optimization [33][34][35], selection optimization of vector methods based on program parallelism features [36], and vector recognition optimization based on directed graph reachability [37]. In addition, SLP methods have also been applied in the fields of dynamic code conversion [38] and optimization of vector code in inline assembly form [39], etc.…”

Section: Wireless Communications and Mobile Computingmentioning

confidence: 99%

An SLP Vectorization Method Based on Equivalent Extended Transformation

Feng

Tao

et al. 2022

Wireless Communications and Mobile Computing

View full text Add to dashboard Cite

SIMD extensions provide an efficient energy consumption platform to support mobile systems. How to use SIMD instructions to improve program performance is a challenge. SLP (superword level parallelism) is an efficient solution to exploit the parallelism, oriented to SIMD, between statements in the basic blocks, and it has been widely used in almost all the mainstream compilers. SLP relies on finding isomorphic statements to pack together into vectors. However, the capability of autovectorization for nonisomorphic statements is insufficient. In this paper, we introduce SLP-E, a novel autovectorization method that can automatically vectorize the codes which contain nonisomorphic statements, translate the nonisomorphic statements into the isomorphic statements by equivalent extended transformation of expressions, and vectorize the isomorphic statements. SLP-E improves the application scope and benefits of SLP. We implement the SLP-E in LLVM and compare it with prior approaches. A set of applications that benefit from autovectorization are taken from the SPEC CPU 2017 benchmark to compare our approach and prior techniques. Experimental results show that SLP-E achieves more than 43.9% speedup, on average, over other similar methods.

show abstract

Revec: program rejuvenation through revectorization

Cited by 13 publications

References 29 publications

MIMD Programs Execution Support on SIMD Machines: A Holistic Survey

MIMD Programs Execution Support on SIMD Machines: A Holistic Survey

Cross-Feature Transfer Learning for Efficient Tensor Program Generation

An SLP Vectorization Method Based on Equivalent Extended Transformation

Contact Info

Product

Resources

About